Leading chipmakers in recent years spent tens of billions of dollars on advanced-chip-packaging facilities-to prepare for building processors in multi-chiplet packages that will offer consistent performance increases and ensure continuity of Moore's law.

The ecosystem for commercial chiplets-one where a marketplace of chiplets from many vendors can be incorporated into a multichip SoC by multiple packaging vendors with mix-and-match ease-has yet to appear.

Lin Jun-cheng, a veteran engineer who worked for TSMC for nearly 19 years, has been hired by Samsung as a vice president.

The US Department of Defense (DoD) is Intel Foundry Services' (IFS's) "No. 1" customer, IFS president Randhir Thakur told EE Times, noting that IFS plans to be part of the DoD state-of-the-art heterogeneous integrated packaging (SHIP) program. That program will necessitate deep knowledge of gate-all-around (GAA) technology facilitating high-transistor-density 3D chips.

SK Hynix aims to select a US site for its advanced chip packaging plant and break ground there around the first quarter of next year, two people familiar with the matter said, helping the United States to compete as China pours money into the burgeoning sector.

Italy is close to clinching a deal initially worth $5 billion with Intel to build an advanced semiconductor packaging and assembly plant in the country, two sources briefed on discussions told Reuters on Thursday.

Intel and Italy are intensifying talks over investments expected to be worth around 8 billion euros ($9 billion) to build an advanced semiconductor packaging plant, two sources close to the matter told Reuters.

Tianshu Zhixin said in January that BI was made using an unidentified 7nm process node and 2.5D chip-on-wafer-on-substrate (CoWoS) packaging. On Wednesday, it confirmed our suspicion that BI was made using TSMC's 7nm FinFET process.

Average delivery times of Kulicke and Soffa Industries' packaging equipment, which require microcontrollers, have doubled to six months, said executive VP Chan Pin Chong. The company supplies equipment to customers like ASE Technology, the world's largest chip packaging and testing services provider.

Siemens and ASE are developing a single platform from 2.5D and 3D packaging to fan-out wafer-level packaging (FOWLP) technologies.

The remarks could signal a shift in focus at the Shanghai foundry which has seen its chances of closing the tech gap with bigger rival TSMC hurt by US sanctions

Google and AMD will be among the first clients for TSMC's new SoIC chips, which use a new 3D technology to stack and link different types of chips in one package. The new chip packaging approach is meant to make the chipset smaller but more powerful and energy efficient.

The trio of techniques aim to give Intel's processors an edge at a time when advances in conventional silicon scaling are slowing and getting more expensive. They arrive as rival TSMC expands its portfolio of chip stacks, and two consortia hope to set standards in the area.

It will be interesting to see whether Samsung Electronics will be able to win back Apple's orders and expand its foundry and non-memory businesses by strengthening its competitive edge in packaging.

Korean semiconductor packager Nepes has become the world's first to commercialize fan-out panel level package (FO-PLP) technology.

Samsung plans to adopt 2.5D and fan-out packaging technologies at the new complex. Taiwan's TSMC was the first to commercialize the fan-out packaging, adopting it to Apple's A Series processors.

Several packaging houses are developing the next wave of high-density fan-out packages for premium smartphones, but perhaps a bigger battle is brewing in the lower density fan-out arena.

With this acquisition, KLA-Tencor will significantly diversify its revenue base and add $2.5 billion of addressable market opportunity in the high-growth PCB, FPD, packaging, and semiconductor manufacturing areas.

Today, Intel announced the delivery of a 17-qubit superconducting test chip for quantum computing to QuTech, Intel's quantum research partner in the Netherlands. The new chip was fabricated by Intel and features a unique design to achieve improved yield and performance.

Jianguang Asset Management (JAC Capital), Leadcore Technology, Qualcomm (China) and Wise Road Capital have signed an agreement to form a joint venture - JLQ Technology - which will focus on the design, packaging, testing, customer support and sales related to chipsets for mass-tier smartphones designed and sold into China.

One of a handful of startups aiming to attack Broadcom's dominance in Ethernet switching emerges from stealth mode this week. Nephos spun out of Taiwan's Mediatek and will push packaging technology from TSMC to a new level.

Given Apple's focus on pushing the performance of its silicon, and TSMC's packaging advancements, it makes sense that TSMC has been able to gain sole possession of Apple's chip orders for at least this generation.

Power component designer Sarda Technologies in the US is teaming up with Asian assembly firm UTAC to use its Heterogeneous Integrated Power Stage (HIPS) in UTAC's 3D SiP based on technology from German embedded board provider AT&S to improve the energy efficiency of data centers.

Advantest has installed its 800th V93000 Port Scale RF test system, with the landmark unit going into the production facility of Jiangsu Changjiang Electronics Technology (JCET), a leading Chinese semiconductor packaging assembly and test company.

STATS ChipPAC has announced that Cavendish Kinetics, a provider of RF MEMS tuning solutions for LTE smartphones and wearable devices, has adopted its advanced wafer level packaging technology to deliver Cavendish's SmarTune RF MEMS tuners in the smallest possible form factor, as a 2mm2 chip scale package.

Toshiba has expanded its package line-up of interface-converter bridge LSIs for high resolution LCD display that are used in tablets, Ultrabooks and other applications.

"Solid demand for wireless communications in both packaging and test was the key driver of our business in the third quarter," said Ken Joyce, Amkor's president and CEO. "Lower-than-anticipated supply of 28nm wafers in the early part of the quarter and the overall weakness in the semiconductor market and general economy constrained our growth."

This achievement was driven by STATS ChipPAC's proven high volume manufacturing capabilities combined with the company's engineering focus on copper wire technology development for a broad range of advanced, multi-die laminate and leaded packages including three dimensional (3D) packaging.

STMicroelectronics is the first company in the world that mass-manufactures MEMS microphones in plastic packages. The patented technology breakthrough saves space and increases durability in consumer and professional voice-input applications, from mobile phones and tablets to noise-level meters and noise-cancelling headphones.

Market research organization DisplaySearch recently estimated Taiwan's LED makers to see profit climb in the second due to ramping shipments of LED backlights for LCD TVs and tablet PCs, rising LED prices and new packaging technologies bringing cost down.

Applied Materials and the Institute of Microelectronics (IME), a research institute under the Agency for Science, Technology and Research (A*STAR), have officially opened the Centre of Excellence in Advanced Packaging at Singapore's Science Park II.

Amkor Technology has announced that its innovative through mold via (TMV) package-on-package (PoP) solutions have surpassed 100 million units shipped.

The US Supreme Court left intact a ruling that lets Tessera Technologies seek damages from Qualcomm and four other companies for infringing patents covering computer-chip packaging.

X-FAB Silicon Foundries and Senodia Technologies (Shanghai) announced they have concluded development and are ramping production of microelectromechanical system (MEMS) gyroscopes for high-volume consumer applications.

Texas Instruments (TI) has shipped more than 30 million units of its PowerStack packaging technology, which significantly boosts performance, lowers power and improves chip densities in power management devices.

The move leaves some to wonder if the silicon foundry giant is gradually moving into the IC-packaging world, thereby competing against Amkor, ASE and other subcontractors. Rick Cassidy, president of TSMC North America, said TSMC remains focused on the foundry market. But "lines are blurring" between some parts of the wafer manufacturing and packaging processes, Cassidy said.

Shares of Tessera Technologies, which owns and makes money licensing numerous patents for combing computer chips together, are up 7% at US$22.09 after an appeals court ruled in favor of the company in its suit against Qualcomm, Spansion and STMicroelectronics.

"Although discussions are ongoing with Sony and Renesas Electronics to secure their continued access to our semiconductor packaging technology through a licensing relationship with us, these discussions have not sufficiently advanced, thus necessitating this lawsuit," said Henry Nothhaft, chairman and CEO of Tessera.