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Global Unichip to volume produce 40nm PCIe Gen2 IP by end of 2009

Press release; Meiling Chen, DIGITIMES [Tuesday 11 August 2009]

Global Unichip has announced that its recent success on Taiwan Semiconductor Manufacturing Company (TSMC)'s 40nm G process PCIe Gen2 IP has been validated in the data rate that ranges from 1Gbps to 6.25Gbps, while it consumes less than 100mW per lane. Furthermore, the company plans to unveil a series of Gbps interface IP solutions, including DDR2/3, SATA, USB3.0, XAUI, and 10G SERDES by the end of 2009.

Global Unichip has firstly introduced its Gbps-level high-speed total solution that includes comprehensive IP portfolio, ASIC implementation, chip with package co-design, and production testing solution targeting high speed networking, video processing, and mobile handset segments.

Global Unichip's high speed interface design flow ensures challenges including signal integrity, bus skew control, system jitter compensation, power delivery network, and overall power reduction are resolved at early stages in an ASIC design cycle, according to the company. The package substrate design follows immediately after chip's floorplan is finished. This allows the packaging model to be referenced by ASIC designers in order to verify the design specifications at the earliest possible stage, the company indicated.


The DIGITIMES editorial staff was not involved in the creation or production of any sponsored content or press release provided in the commercial news wire service. Companies looking to contribute commercial news or press releases are welcome to contact us.

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