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News tagged Cadence
  • Last update: Wednesday 26 October 2016 [44 news items]

Cadence IP tools certified on Samsung 10nm process technology

Oct 26, 11:52

Cadence Design Systems has announced that its complete suite of digital and signoff tools has been certified for Samsung Electronics' Process Design Kit (PDK) and Foundation Library...

Fujitsu adopts Cadence Palladium Z1 enterprise emulation platform

Oct 24, 23:25

Cadence Design Systems, has announced that Fujitsu has adopted the Cadence Palladium Z1 enterprise emulation platform for the development of the ARMv8-based Post-K computer. The Post-K...

Cadence, TSMC advance 7nm FinFET designs for mobile and HPC platforms

Sep 26, 15:00

Cadence Design Systems has announced several important deliveries in its collaboration with TSMC to advance 7nm FinFET designs for mobile and high-performance computing (HPC) platf...

Cadence delivers integrated system design solution for TSMC InFO packaging technology

Sep 23, 10:55

Cadence Design Systems has announced the immediate availability of an integrated system design solution for TSMC's advanced wafer-level integrated fan-out (InFO) packaging technology,...

Cadence delivers tools for implementation and signoff of new ARM Cortex-R52 CPU

Sep 21, 11:00

Cadence Design Systems has announced the availability of a Cadence Rapid Adoption Kit (RAK) for the new ARM Cortex-R52 CPU, which targets complex embedded designs for safety applications...

Micron intros SLC NAND flash for IoT and automotive

Jul 15, 16:02

Micron Technology has announced its newest embedded SLC NAND flash optimized for the next generation of Internet of Things (IoT) and automotive applications. Available with differing...

Intel certifies Cadence implementation and signoff tools for 10nm tri-gate process

Jul 13, 22:15

Cadence Design Systems has announced that its implementation and signoff tools have been certified on the Intel third-generation 10nm tri-gate process for customers of Intel Custom...

Cadence delivers rapid adoption kit based on 10nm reference flow for new ARM Cortex-A73 CPU and ARM Mali-G71 GPU

May 30, 14:28

Cadence Design Systems has announced the availability of a Rapid Adoption Kit (RAK) based on the ARM internal flow used for the design of the ARM Cortex-A73 central processing unit...

Cypress adopts Cadence design tools for 40nm auto ICs

May 12, 13:46

Cypress Semiconductor has selected the full Cadence RTL-to-signoff digital design flow and complete Spectre circuit simulation platform for all of its 40nm automotive chip designs,...

Toshiba adopts Cadence Innovus implementation system for memory controller design

Apr 26, 10:57

Toshiba has adopted the Cadence Innovus implementation system for its memory controller's production design project, according to the EDA company. The tool enabled Toshiba...

UMC qualifies Cadence Virtuoso LDE analyzer for its 28HPC process

Apr 14, 14:41

Cadence Design Systems has announced that the company's Virtuoso layout-dependent effects (LDE) analyzer has been qualified by United Microelectronics (UMC) to support the foundry's...

Cadence digital and signoff tools certified on Samsung 14LPP process

Mar 31, 08:53

Cadence Design Systems has announced that its complete suite of digital and signoff tools has achieved certification for Samsung Foundry's process design kit (PDK) and foundation...

Cadence design tools certified for TSMC 7nm design starts and 10nm production

Mar 17, 11:13

Cadence Design Systems has announced that its digital, signoff and custom/analog tools have achieved V1.0 Design Rule Manual (DRM) and SPICE certification from TSMC for its 10nm FinFET...

Cadence launches complete IC packaging design and analysis solutions for fan-out WLCSP

Mar 16, 11:03

Cadence Design Systems has announced the availability of foundry-proven IC packaging design and analysis solutions for advanced fan-out wafer-level chip scale packaging (WLCSP) and...

Cadence unveils Virtuoso platform for 10nm processes

Dec 3, 11:19

Cadence Design Systems has announced the delivery of the new Virtuoso advanced-node platform that is enabled for all 10nm FinFET designs. This next-generation custom design platform...

Cadence announces tools enabled for Globalfoundries 22FDX platform

Nov 10, 15:42

Cadence Design Systems has announced that its digital and signoff tools are now enabled for the current version of the Globalfoundries 22FDX platform reference flow. Globalfoundries...

Cadence announces memory model for LPDDR5

Oct 13, 14:39

Cadence Design Systems has announced the Cadence Memory Model for the LPDDR5 standard. This new verification IP (VIP) product enables engineers to verify that system-on-chip (SoC)...

Imec and Cadence complete tapeout of first 5nm test chip

Oct 8, 10:08

Nano-electronics research center imec and Cadence Design Systems have announced that the companies completed the first tapeout of a 5nm test chip using extreme ultraviolet (EUV) as...

Cadence offers design tools for TSMC InFO packaging

Sep 23, 15:58

Cadence Design Systems has announced that its Allegro system-in-package (SiP) and physical verification system (PVS) implementation technologies have been enabled for TSMC's integrated...

Cadence announces IP portfolio for TSMC 10nm FinFET process

Sep 17, 15:46

Cadence Design Systems has announced an intellectual property (IP) portfolio for TSMC's 10nm FinFET (N10) process. Cadence has already secured multiple design wins with this portfolio...

Realtek accelerates SoC verification with Cadence Palladium XP platform

Aug 11, 20:07

Cadence Design Systems has announced that Realtek Semiconductor utilized the Cadence Palladium XP platform to accelerate the development and verification of a recent system-on-chip...

Cadence, TSMC collaborate on IoT IP subsystem

Jun 9, 11:20

Cadence Design Systems has announced that it is collaborating with TSMC on the development of an Internet of Things (IoT) IP subsystem demonstration platform for TSMC's ultra-low...

Cadence implementation and signoff tools certified on Intel 14nm Process

Jun 5, 15:09

Cadence Design Systems has announced that its implementation and signoff tools have achieved certification on the Intel 14nm process for customers of Intel Custom Foundry. Intel Custom...

Globalfoundries announces design infrastructure for 14nm FinFET process

Jun 3, 12:15

In collaboration with design ecosystem partners, Globalfoundries has announced the availability of digital design flows for customers designing on its latest manufacturing technology...

Cadence digital and custom/analog tools achieve TSMC certification for 10nm FinFET early design starts

Apr 9, 22:07

Cadence Design Systems has announced that its digital and custom/analog tools have achieved certification from TSMC for its most-current version of 10nm FinFET Design Rule Manual...

Cadence and Intel collaborate to release 14nm library characterization reference flow

Mar 18, 15:15

Cadence Design Systems and Intel have delivered a 14nm library characterization reference flow for customers of Intel Custom Foundry, continuing their collaboration on enabling digital...

Global Unichip utilizes Cadence analog IP to implement WiGig-enabled SoC on 28nm process

Mar 5, 22:17

Cadence Design Systems has announced that Global Unichip achieved first-silicon success integrating tri-band analog front-end (AFE) intellectual property (IP) with WiGig (IEEE 802.11ad),...

UMC and Cadence collaborate to deliver 28nm design reference flow for ARM Cortex-A7 MPCore-based SoC

Jan 21, 13:49

Cadence Design Systems has announced that United Microelectronics (UMC) used its implementation and signoff tools to produce a silicon-ready 28nm ARM Cortex-A7 MPCore-based System-on-Chip...

Globalfoundries and Cadence deliver first SoC enablement solution featuring ARM Cortex-A17 processor in 28nm-SLP process

Dec 18, 21:58

Cadence Design Systems and Globalfoundries have jointly announced the delivery of quad-core silicon built around the ARM Cortex-A17 processor implemented using Globlfoundries' 28nm...

HiSilicon expands adoption of Cadence tools and IP for advanced-node FinFET designs

Dec 2, 14:38

Cadence Design Systems announced on December 1 that HiSilicon Technologies has signed an agreement to significantly expand its use of the Cadence digital and custom/analog flows for...

VIA licenses Cadence Tensilica HiFi audio/voice DSP

Oct 23, 11:08

Cadence Design Systems has announced that VIA Technologies has selected the Cadence Tensilica HiFi audio/voice digital signal processor for a system-on-chip design for set-top boxes,...

ARM buys mobile display IC cores from Cadence

Sep 4, 15:02

Processor IP licensor ARM and Cadence Design Systems, an EDA tool company, have signed an agreement for the sale and transfer of Cadence PANTA display controller cores to ARM, according...

Blue-collar processing: Q&A with Tensilica founder Chris Rowen

Jun 28, 16:12

Based in Santa Clara, Tensilica has been around the semiconductor industry for around 15 years, providing customers with what it calls configurable dataplane processors (DPUs). The...

Chris Rowen, chief technology officer and founder of Tensilica<br>

20nm process to take off in 2013, says Cadence executive

Apr 19, 15:15

The semiconductor industry will accelerate towards the adoption of 28nm process in 2012, and begin its transition to the next technology node in 2013, according to Chi-Ping Hsu, a...

Globalfoundries tapes out 20nm test chip

Aug 30, 16:40

Globalfoundries has announced that it successfully taped out a 20nm test chip using flows from EDA partners Cadence Design Systems, Magma Design Automation, Mentor Graphics and Synopsys...

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