JEDEC Solid State Technology Association has announced the publication of several key updates to the Universal Flash Storage (UFS) family of standards. These include JESD220C UFS version 2.1, JESD223C UFSHCI version 2.1, JESD220-1A UFS UME version 1.1 and JESD223-1A UFSHCI UME version 1.1.

JEDEC Solid State Technology Association has announced the publication of Release 6 of the DDR3 Serial Presence Detect (SPD) document. The updated standard describes new memory timing parameters and enables higher capacity memory modules.

Toshiba has developed what it claims is the world's fastest device controller for embedded NAND flash memory modules compliant with the Universal Flash Storage (UFS) Ver.2.0 and UFS Unified Memory Extension (UME) Ver.1.0 standards defined by JEDEC Solid State Technology Association (JEDEC).

Just as its predecessors did, the LPDDR4 specification is aiming to double its data rates while slashing power consumption in half, but first publication of the spec by JEDEC won't be until 2014.

JEDEC has announced the publication of Universal Flash Storage (UFS) version 2.0, which offers performance and power saving features over the prior version of the standard.

JEDEC Solid State Technology Association has announced that its board of directors appointed two new members, Jong H. Oh of SK hynix and Hung Vuong of Qualcomm.

Agilent Technologies has launched the N6465A test application for embedded multimedia card (eMMC) compliance test in response to a new version of the JEDEC eMMC specification.

JEDEC Solid State Technology Association has announced the availability of a new standard for wide I/O mobile DRAM: JESD229 wide I/O single data rRate (SDR).

JEDEC Solid State Technology Association has announced a broad spectrum of ongoing standards development work related to 3D-ICs.

MO-300 defines the dimensions, layout and connector position for very small form factor (50.8x29.85mm) SSDs with the new mini-SATA interface connector. Supporting 1.5Gb/s and 3.0Gb/s data transfer rates, the mSATA connector is designed especially for netbooks and other portable electronics devices.

Synopsys has announced that its DesignWare DDR3/2 PHY and digital controller IP is the first DDR3 IP that has been fully verified in test silicon at 1600 Mbps, the maximum data-rate of the JEDEC DDR3 specification. DesignWare DDR3/2 PHY and the digital controller IP are available now in advanced process technologies for foundries.