The intellectual property dispute between Corning and China-based IRICO has entered a new phase at the U.S. International Trade Commission (ITC), with the focus shifting from the finding of trade secret misappropriation to potential remedies affecting access to the U.S. market.On July 23, an ITC Administrative Law Judge (ALJ) issued an Initial Determination finding that IRICO and the remaining respondents had misappropriated Corning trade secrets related to its fusion glass manufacturing technology. The judge followed with a recommended remedy on August 6, and on August 7 the ITC issued a public interest notice disclosing part of that recommendation, including a proposed Limited Exclusion Order (LEO) against IRICO and the remaining respondents.The August 7 notice provided the first meaningful public indication of the remedies being considered. When the Initial Determination was announced in July, only limited information was available publicly. For Corning, the notice marks an important step toward potential enforcement measures following the ALJ's finding that its fusion-draw trade secrets had been misappropriated."Corning welcomes the initial determination and recommended exclusion order by the International Trade Commission. The determination makes clear that IRICO misappropriated Corning's proprietary fusion-draw technology, underscoring the value of Corning's innovations," said Brendan Mosher, International Vice President and General Manager, Corning Display Technologies."Protecting our intellectual property reflects our Values and our commitment to doing what's right for the last 175-years. Through these actions, we are safeguarding our innovations, our people, and our ability to do what we do best: transform industries, support our customers, and improve lives."Ruling Extends to Manufacturing and Downstream ProductsThe July 23 Initial Determination found that IRICO had misappropriated key Corning trade secrets related to fusion glass manufacturing, with the technology at issue broadly used across IRICO's glassmaking operations. The ruling did not narrow its scope based on glass generation size, glass composition, or other product-specific conditions, and applied to the remaining respondents in the case, including TCL, CSOT, and CHOT.That distinction is important because the central issue of misappropriation is not simply which glass formulation is being used, but how the glass is manufactured. If the final determination follows the current direction, changing a glass composition or product specification alone would be unlikely to provide IRICO with a workaround.Exclusion Order Raises the Stakes for Display ManufacturingThe August 7 public interest notice confirmed that the ALJ recommended a Limited Exclusion Order restricting U.S. imports of display products containing IRICO glass. For Corning, the significance of the remedy lies in how a dispute over manufacturing technology can carry through the broader display production chain.Display glass sits near the beginning of that chain. Once produced, the substrate moves through panel fabrication, module integration, and system assembly before ending up in televisions and other finished products. Because the case centers on the fusion manufacturing technology used to make the glass rather than on a single composition, Corning believes the ruling creates significant risk for customers that continue to source IRICO glass for products intended for the U.S. market.Corning is also seeking review of the recommended multi-year exclusion period, arguing that the evidence presented in the case supports a longer duration and that the final Commission determination could ultimately impose a longer restriction.Corning Seeks Review of Limited IssuesCorning has petitioned the full Commission to review several narrowly defined issues. Corning's petition does not challenge the central finding that IRICO misappropriated Corning's fusion technology, nor does it challenge the issuance of an exclusion order. Instead, they focus on clarifying the transparent process Corning has taken to protect intellectual property rights and support the growth of the display industry in China and across the globe."While we appreciate the ALJ's confirmation that IRICO misappropriated Corning's technology, as well as the recommended exclusion order, Corning is seeking review of certain statements in the determination ," said Mosher."We have consistently acted with transparency, integrity, and responsible stewardship of its innovations, while supporting the growth of the display industry, and will continue to take all appropriate steps to protect Corning's intellectual property."Corning maintains that it clearly and consistently communicated its concerns related to IRICO's misappropriation of its trade secrets, preserved its right to seek remedy, and presented substantial evidence in this regard.In addition, Corning maintains its course of action over the years with respect to IRICO and the display industry was reasonable and considerate, and that it had continuously taken measures over the years to protect its trade secrets.Commission Review Comes NextThe case has not yet reached a final ITC determination. Following the ALJ's Initial Determination, the full Commission reviews the decision and ultimately issues the Commission's Final Determination. Corning's current petitions are part of that process and identify the limited issues it wants the Commission to reconsider.Corning is also reiterating that intellectual property protection remains a fundamental part of its long-term research and innovation strategy. The company emphasizes that invention and innovation have been at the core of its business for 175 years and that its intellectual property reflects sustained investments in R&D, technology development, and industry collaboration. When it identifies unauthorized use or misappropriation of its technology, Corning says it will take the necessary steps to protect those investments.As the fusion trade secret case moves through Commission review, Corning will continue taking appropriate steps to protect its intellectual property while supporting the continued growth and development of the display industry.

With more than 35 years of experience in ASIC design services, Progate Group Corporation (PGC, TPEx: 8227), a member of the TSMC Design Center Alliance (DCA) and a Synopsys IP OEM Program partner, provides cost-effective and flexible ASIC turnkey services to help startups and enterprises overcome the barriers to customized chip development and accelerate their products from concept to mass production.PGC's integrated development path covers IP licensing, IP integration, IC design, physical implementation, tape-out, manufacturing, packaging, testing, and mass production - combining its ASIC design expertise with the TSMC ecosystem and Synopsys IP resources. PGC's website states that the company has taped out more than 1,500 projects at TSMC and supports both CyberShuttle/MPW and mass-production services.As artificial intelligence (AI) and high-performance computing (HPC) applications continue to expand, demand for customized ASICs is increasing across a wide range of applications, including AI acceleration, Edge AI, networking, and other computing applications. However, high non-recurring engineering (NRE) costs, complex IP integration, and lengthy development cycles remain major challenges for companies seeking to develop their own chips.Lowering the Barriers to ASIC DevelopmentASIC development has traditionally been dominated by large enterprises with significant semiconductor resources and engineering capabilities. With the rapid growth of AI applications, however, more startups and enterprises are looking to develop customized chips to achieve better performance, lower power consumption, and improved cost efficiency.PGC addresses these challenges through its one-stop ASIC turnkey service, giving customers access to the expertise and resources required throughout the chip development lifecycle without having to build a complete ASIC development organization internally.Through the Synopsys IP OEM Program, PGC also provides access to cost-competitive IP solutions and supports the integration of high-speed interface and other semiconductor IP, helping customers reduce IP licensing costs, simplify development, and shorten the overall design cycle. PGC's current service portfolio includes high-speed interface IP integration such as PCIe, USB, MIPI, SerDes, DDR, and die-to-die interfaces.Case Study 1: AI Startup Accelerates FPGA-to-ASIC Migration with MPW/Shuttle FlowAn AI startup specializing in image recognition initially used FPGA technology for product development. As market demand grew, the company faced increasing cost and power-consumption challenges, making the FPGA-based solution less suitable for large-scale production.After engaging PGC, the company transitioned from FPGA to ASIC through PGC's FPGA-to-ASIC solution. To reduce the initial development cost and lower the risk of ASIC adoption, the customer adopted an MPW/Shuttle flow for the first silicon implementation. PGC also integrated multiple high-speed interface IPs and managed the ASIC design flow from development through tape-out.The project achieved First Silicon Success on the first tape-out, along with a significant reduction in power consumption, an approximately 10 percentage reduction in overall cost, and an approximately 20 percentage reduction in time-to-market compared with the company's original FPGA-based development timeline.The project demonstrates how PGC's FPGA-to-ASIC solution and MPW/Shuttle flow can help AI startups reduce initial development costs and technical risks while providing a practical path from FPGA prototyping to ASIC implementation and subsequent mass production.PGC's existing service model supports the transition from smaller-volume MPW/CyberShuttle runs to full-mask development and high-volume production, allowing customers to select an appropriate development path as their products mature.Case Study 2: Edge AI Company Develops a Customized SoCAn Edge AI company sought to develop a customized SoC to meet growing demand for intelligent edge applications. Compared with conventional off-the-shelf solutions, a customized chip offered better integration, lower power consumption, improved performance, and greater flexibility for the company's target applications.Developing an ASIC requires expertise across system architecture, IP selection and integration, IC design, physical implementation, manufacturing, and testing. The company therefore sought an experienced ASIC partner to accelerate development while managing overall project cost and risk.PGC provided a comprehensive turnkey solution covering system architecture planning, IP integration, IC design, physical implementation, tape-out, manufacturing, packaging, and testing. By integrating the required IP and managing the development flow end to end, PGC helped the customer move efficiently from system requirements to a finished customized SoC.The result was improved system integration and performance, reduced overall system cost, and better power efficiency, giving the customer greater flexibility to optimize its chip for specific Edge AI applications.This case demonstrates PGC's ability to support not only AI startups but also companies developing next-generation Edge AI solutions, helping them build in-house customized chip capabilities and strengthen long-term product competitiveness.PGC has specifically highlighted FPGA-to-ASIC migration and Edge AI SoC development as important application areas, with its turnkey platform covering front-end design, back-end APR, tape-out, MPW/CyberShuttle runs, and subsequent production.Flexible ASIC Turnkey Services for Different Development NeedsPGC offers a flexible development model designed to support projects of different sizes and stages. Customers can choose from multiple development and manufacturing models, including MPW/Shuttle services, mass production (MP), and Customer-Owned Tooling (COT), allowing them to select an approach that matches their budget, production requirements, and long-term business strategy.For startups and companies entering ASIC development for the first time, an MPW/Shuttle flow can provide a practical and cost-effective approach for initial silicon development and validation. By sharing wafer costs across multiple projects, MPW can help reduce the upfront cost of producing prototype silicon compared with a dedicated full-mask approach.As products mature and production volumes increase, PGC can support customers in transitioning from prototype silicon to mass production. Its turnkey service covers the broader supply chain, including wafer fabrication, CP/FT testing, packaging, and production support.Through its one-stop turnkey model, PGC can coordinate IP, design, foundry, packaging, and testing resources, helping customers reduce project complexity and focus on their core product and application development.Combining TSMC, Synopsys and OSAT Ecosystem ResourcesPGC's turnkey model is built around close collaboration with major semiconductor ecosystem partners. As a certified member of the TSMC Design Center Alliance, PGC provides TSMC ASIC design and CyberShuttle services. The company also works with Synopsys through the IP OEM Program and collaborates with ASE and other OSAT partners for packaging and testing.This ecosystem-based approach allows PGC to integrate design, IP, manufacturing, packaging, and testing resources into a coordinated development flow. For startups and small and medium-sized companies, this can reduce the need to independently manage multiple semiconductor suppliers and technical interfaces throughout the ASIC development process.PGC also supports advanced-node ASIC development. Its current service portfolio includes TSMC 6nm, 5nm, 4nm, and 3nm FinFET processes, as well as advanced packaging services such as CoWoS.Looking AheadPGC plans to deepen its collaboration with ecosystem partners while expanding IP integration and advanced-process design capabilities, including support for more advanced TSMC process nodes and continued growth of its Synopsys IP OEM offerings.The company will continue to focus on helping startups and enterprises move from FPGA or off-the-shelf solutions toward customized ASIC architectures, particularly for AI, Edge AI, HPC, networking, and other high-growth applications.By combining ASIC design expertise, TSMC ecosystem resources, Synopsys IP access, and flexible MPW/Shuttle, MP, and COT models, PGC aims to help more companies overcome the traditional barriers to ASIC development.The goal is to lower development risk and cost, accelerate time-to-market, and provide a practical path from initial silicon development to mass production - enabling more startups and enterprises to build customized AI and Edge AI chips and strengthen their long-term product competitiveness.For more information, please visit the official website.

As demand for AI servers, high performance computing (HPC), and data center infrastructure accelerates, the semiconductor and power electronics test equipment market is experiencing strong growth. This momentum is expected to continue as advanced semiconductor technologies drive increasingly sophisticated testing requirements.Chroma ATE Inc., a company with more than two decades of experience in automated test equipment (ATE), recently held its Semiconductor Test Equipment User Conference in Hsinchu, Taiwan. Registration quickly reached capacity, reflecting the company's growing prominence in the semiconductor testing market. In 2025, Chroma reported consolidated revenue of US$943 million and grew its global workforce to nearly 4,000 employees.Credit: ChromaAddressing the Testing Challenges of the AI Era with In-House InnovationGeorge Chang, President of Chroma's Semiconductor Test Equipment Business Unit (STE BU), emphasized that Chroma is one of the few ATE suppliers with the in-house capability to develop  application-specific integrated circuits (ASICs) for its own test systems. This capability creates a "technology moat" that reinforces Chroma's competitive advantage.To address the diverse needs of the semiconductor testing market, Chroma has built its portfolio around three specialized test platforms. The Chroma 3680 is designed for advanced devices used in AI, HPC, microcontroller unit (MCU), and mixed-signal applications, the Chroma 3650 addresses power devices and systems-on-chip (SoCs), and the Chroma 3380 targets mainstream MCUs, Internet of Things (IoT) devices, and other chips manufactured on mature process nodes. Combined shipments across the three platforms have exceeded 4,000 systems. This year, Chroma also introduced the compact Chroma 3650-S2C platform for high-power devices, responding to increasingly rapid product cycles across the semiconductor industry.Proprietary PINF ASIC Enables Seamless Migration for Complex SoC TestingAs AI and HPC drive more complicated chip designs, testing is becoming more diverse and technically more demanding. At the same time, the industry is facing growing pressure to reduce costs and shorter test development schedules. Spancer Lee, Senior Manager of product marketing at Chroma's STE BU, explained that the Chroma 3680 integrates Chroma's next-generation, self-developed PINF ASIC with a range of specialized system boards, each supporting different test functions. This architecture enables comprehensive coverage across four major testing domains: digital, analog, mixed-signal, and RF devices. Chroma plans to continue expanding the platform's capabilities, leveraging the flexibility of its in-house hardware development to support high-precision testing of increasingly complex and high-frequency SoC devices. To accommodate the intensive data transfer and processing requirements involved with testing advanced semiconductor devices, the Chroma 3680 employs an 8-lane, 20 Gbps parallel high-speed data architecture. Optimized firmware enables high-speed transfer and more efficient processing of complex test data. The architecture also minimizes synchronization latency between digital and analog resources, improving resource integration for highly complex SoC test programs.The Chroma 3680 architecture is also compatible with certain probe card models used on competitor platforms. This allows customers to retain existing load boards and test programs without modifying their hardware, reducing migration costs while maximizing ROI and helping chipmakers gain a competitive edge in the market.Credit: ChromaChroma 3650-S2C Delivers High-Voltage Capability in a Compact FootprintWith NVIDIA signaling a transition toward direct 800V DC power delivery for server racks, semiconductor manufacturers face growing demand for high-voltage testing. To address this need, Chroma developed the 3650-S2C, a new test platform optimized for high-power semiconductor devices including silicon carbide (SiC) and gallium nitride (GaN). Through extensive engineering refinement, the platform's slot count was reduced to six, optimized for the requirements of intermediate-level testing. Chroma also substantially streamlined the external high-voltage power rack by integrating it directly into the test head. The 3650-S2C cuts the system footprint by half, enabling seamless integration with mainstream turret handlers for volume production while helping OSAT partners save valuable factory space and infrastructure costs.Aaron Chuang, Senior Manager of Advanced Technology Development at Chroma's STE BU, highlighted two key characteristics of the Chroma 3650-S2C: powerful high-voltage capability and a compact footprint. Building on the proven Chroma 3650-S2 platform, the solution integrates a high-voltage source-measurement unit (HVSMU) board to deliver a comprehensive, one-stop solution for five critical test parameters. It enables customers to safely and accurately overcome the 4 kV test threshold while maintaining production throughput, providing a powerful foundation for next-generation high-voltage power semiconductors to advance into mass production.Credit: ChromaIntegrated High-Density RF Technology Addresses Next-Generation Ultra-High-Frequency Wireless TestingThe rapid adoption of AI, edge computing, and intelligent connected devices continues to drive growth across Wi-Fi, Bluetooth, GNSS, IoT, mobile, and wearable applications. At the same time, wireless communication chipsets are undergoing a significant generational upgrade.To address these evolving requirements, Chroma has integrated its new HDRF3 (high-density radio frequency) test module into the Chroma 3680 platform. The solution is designed to support the increasing bandwidth, advanced modulation schemes, and multi-antenna architectures required by next-generation wireless technologies. This positions the company to capture the high-performance networking and AIoT chip packaging and testing markets.According to Jackson Hsu, associate director of application engineering at ADIVIC, a Chroma-affiliated company, Wi-Fi 7 expands channel bandwidth from 160 MHz to 320 MHz while increasing modulation density to 4096-QAM. These advances place exacting demands on RF performance and noise characteristics in test instrumentation. The HDRF3 test module was specifically developed to meet these requirements, extending operating frequencies up to 8 GHz and providing full coverage for Wi-Fi 7 as well as future Wi-Fi 8 implementations.ADIVIC also plans to launch an extension model, the 35809, featuring a simplified 16-port design while maintaining complete software compatibility with the production-oriented HDRF3 platform. The solution is targeted at applications requiring RF IC testing only. Chroma's in-house ASIC expertise allows the company to adapt the hardware architecture of its Chroma 3680, 3650, and 3380 platforms to distinct market requirements. From the space-efficient Chroma 3650-S2C to the high-density HDRF3 module, each development addresses emerging technical challenges across the semiconductor industry.Credit: ChromaThrough a combination of flexibility, high return on investment, and seamless platform migration strategies, Chroma helps customers accelerate adoption while reducing operational barriers. As AI, advanced computing, wireless connectivity, and power semiconductors continue to reshape the industry, Chroma is positioning itself as a long-term strategic partner for the world's leading semiconductor manufacturers.

SK hynix Inc. (or "the company", www.skhynix.com) announced today that its Board of Directors has approved a resolution to repurchase and fully cancel 40 trillion won worth of its own shares. The Company also revealed plans to return "over 50% of cumulative Free Cash Flow (FCF)" generated during the program period (2025-2027), adopting a framework centered on the parallel execution of share repurchases and cancellations alongside cash dividends.Following the Board meeting held earlier today, the Company formally disclosed the share repurchase and cancellation resolution along with the shareholder return plan via a regulatory filing.The decision stems from the assessment that the Company's intrinsic value—underpinned by its business competitiveness, robust cash generation capability, and mid-to-long-term growth potential—is not fully reflected in its current stock price.SK hynix continues to record record-breaking financial performance, maintaining its leadership in the AI memory market. As of the end of the second quarter of this year, the Company's net cash stood at approximately 69 trillion won, demonstrating significantly improved cash generation capability.The total planned amount for the share repurchase is 40 trillion won. Based on the closing stock price of 1,662,000 won on the day prior to the Board resolution, this represents approximately 24.07 million shares, or about 3.3% of total issued shares (730,492,365 shares). The repurchase period is scheduled to run for approximately three months starting August 20, with all repurchased shares set to be cancelled upon completion of the acquisition.This initiative accelerates the execution of the existing shareholder return program ahead of schedule. In November 2024, SK hynix announced a program to execute shareholder returns within the range of 50% of its three-year (2025-2027) cumulative FCF, noting that it would consider early execution prior to the program's expiration if FCF increased meaningfully due to improved operational performance.The 40 trillion won program marks the largest treasury share cancellation ever conducted by a South Korean listed company. The Company noted that progress toward its financial health targets remains on track, affirming its commitment to maintaining a stable financial structure while delivering sustained shareholder value.Through today's regulatory filing, SK hynix announced plans to pursue an expansion of its total shareholder return target from the previous "within 50% of cumulative FCF" to "over 50% of cumulative FCF". Under the framework, shareholder returns will be executed through a dual-track approach running share repurchases/cancellations alongside cash dividends, while options to expand payouts—including the existing fixed dividends and special dividends—are also under consideration.SK hynix emphasized that it intends to pursue additional shareholder returns within the program period through the parallel execution of share repurchases/cancellations and dividends, by taking into account cash flows, market conditions, and distributable profits, adding that specific details regarding scale and execution will be announced following Board approval at the time of its third-quarter earnings release.

For Malaysian engineering students entering their final semesters, the transition from academia to the professional world can feel daunting. Nicholas Tan Peng Gen, a Computer Engineering graduate from Asia Pacific University (APU), found himself at that exact crossroads just a year ago. Today, he is thriving as a Firmware Engineer at Phison Electronics' subsidiary MaiStorage in Malaysia, contributing to semiconductor R&D that powers storage devices globally. In a recent interview, Nicholas shared his journey of landing a role at Phison through the Taiwan Semiconductor Job Fair in Malaysia, the steep but rewarding learning curve of R&D work, and why more Malaysian students should consider global IC design houses like Phison to kickstart their careers.The Gateway: A "Two-for-One" Career OpportunityThe Taiwan Semiconductor Job Fair was organized as part of Taiwan's efforts to strengthen international semiconductor talent connections. Through initiatives supported by Taiwan's Industrial Development Administration (IDA), Ministry of Economic Affairs, Taiwanese semiconductor companies and academic institutions were brought together overseas to connect with promising STEM talents, introduce career opportunities, and build long-term talent partnerships with local universities.Nicholas's journey began when his university lecturers shared details about the Taiwan Semiconductor Job Fair. One lecturer even chartered a bus to ensure the entire class could attend. For Nicholas, who was seeking industry experience but was also curious about further studies, the fair proved to be an eye-opener."It wasn't just a regular job fair. It is an absolute must-attend because it's a rare 'two-for-one' opportunity. You aren't just getting face-to-face access to industrial heavyweights; you're also interacting directly with academic institutions from Taiwan offering funded master's and PhD programs," he said.Walking into the fair, Nicholas secured a direct live screening session, allowing him to have a genuine conversation with Phison's recruitment team rather than simply submitting a resume through an online portal.Shedding "Vibe Coding" for Real-World EngineeringTransitioning from university projects to a global semiconductor firm brought a fundamental shift in perspective. Nicholas noted that in university, students often get by with short-term, loosely structured code as long as it functions by the deadline.At Phison, the standards are stringent. Every line of code must possess meaning, clarity, and purpose so that it remains readable and robust before being deployed on actual hardware. This completely eliminates what modern developers refer to as "vibe coding," because guessing or patching on the fly is highly risky when dealing with complex controller chips. Instead, engineers must trace code step by step and thoroughly understand the system architecture, backed by a rigorous peer-review process where technical logic is closely scrutinized by experienced senior engineers to rapidly accelerate a junior engineer's competence.Why Phison? Full-Stack Architecture Exposure with a Strong Support SystemOne of the key advantages of joining a prominent Taiwanese multinational like Phison from its Malaysian branch is the depth of technical support available. When tackling highly complex technical issues, local teams are never isolated - they have direct access to decades of foundational expertise and the engineering resources of Phison's Taiwan headquarters.Furthermore, rather than being confined to a single, repetitive task, firmware engineers at Phison are given ownership of the full development pipeline. They read and interpret core design specifications, implement advanced features, write testing scripts, verify across multiple hardware platforms, and execute end-to-end debugging. Handling the full pipeline naturally trains engineers to think like system architects, enabling them to see the bigger picture of how their code interacts with physical hardware - making them versatile professionals much faster, Nicholas said.This borderless collaboration also cultivates strong cross-cultural communication skills. Nicholas noted that while Mandarin is commonly used, teams regularly converse in English and utilize translation tools, making the language barrier a manageable factor. Learning to document complete code-tracing workflows for cross-border engineering teams rapidly builds global competitiveness.Life at Phison Malaysia: A 9-out-of-10 ExperienceWhen asked to rate his job satisfaction at Phison Malaysia, Nicholas gave it a 9 out of 10. The semiconductor industry is fast-paced and demanding, but the work environment allows engineers to maintain clear boundaries and protect their personal time. Working at Phison's established branch in Malaysia offers a premier international career path without requiring graduates to relocate away from their families, making it a compelling option for local talent.The company culture also fosters supportive autonomy. Team members are highly collaborative, and while senior engineers are always available to troubleshoot, they challenge junior engineers to bring their own analysis to the table first - fostering independence and professional accountability.Advice to Graduating StudentsAs global demand for semiconductors surges - driven by the explosive growth of AI hardware - Malaysia's semiconductor ecosystem is rapidly moving up the value chain from back-end assembly and packaging into high-value R&D and IC design.For students weighing their next career steps, Nicholas offered one definitive piece of advice regarding the upcoming career fair: "Just go. You might walk out of there with a lot more clarity for your future. Taking on challenges early in your career helps you grow much faster, and the skills you build at an international standard with Taiwanese companies such as Phison are instantly transferable worldwide."From a university student seeking his first career opportunity to a firmware engineer contributing to global semiconductor products, Nicholas's journey demonstrates how international talent engagement can create new pathways for young engineers to connect with Taiwan's semiconductor industry.Through collaboration among Taiwan's semiconductor companies, academic institutions, and global STEM talent communities, more students like Nicholas can discover opportunities within Taiwan's semiconductor ecosystem and contribute to the next generation of semiconductor innovation worldwide.

BIOSTAR, a leading manufacturer of edge AI solutions, industrial motherboards, and edge computing systems, today announces its participation in embedded world North America 2026, taking place September 22–24, 2026 at the Anaheim Convention Center in Anaheim, California, USA. At Booth 6512 in Hall B, BIOSTAR will showcase its latest edge AI and IPC computing solutions, giving visitors a firsthand look at technologies developed for smart manufacturing, smart cities, and smart retail applications.At this year's expo, BIOSTAR will feature a comprehensive portfolio of industrial motherboards and EdgeComp systems, along with live demonstrations designed to address a wide range of edge computing requirements. Highlights include AI IPC solutions powered by Intel Core Ultra platforms, edge AI computing solutions featuring NVIDIA Jetson Orin and Thor platforms, and industrial-grade systems built for dependable deployment across commercial and industrial environments.The industrial motherboard lineup will include the Intel W880, Panther Lake as well as Wildcat Lake platforms. Spanning a range of platform configurations, form factors, and connectivity options, these boards give developers, system integrators, and industrial solution providers a flexible foundation for building application-specific IPC systems.BIOSTAR will also present an extensive selection of EdgeComp systems, including the Intel Panther Lake and NVIDIA Jetson Thor, Jetson Orin edge AI platforms, together with the new WildCat SBC rugged system. Ranging from compact single-board designs to higher-performance networking and gateway platforms, this lineup supports both conventional edge computing workloads and emerging edge AI applications across smart manufacturing, smart cities, and smart retail environments.Live demonstrations will feature the EdgeComp edge AI platforms. Together, these demonstrations will give visitors a practical view of how compact edge platforms can support real-time data processing, intelligent monitoring, and connected industrial applications.BIOSTAR invites industry professionals, system integrators, technology partners, and IPC innovators to visit Booth 6512 in Hall B and experience its latest edge computing and edge AI solutions firsthand. The BIOSTAR team looks forward to connecting with industry peers, discussing emerging application requirements, and exploring new opportunities for collaboration at embedded world North America 2026.

SK hynix Inc. (or "the company", www.skhynix.com) announced today that it has decided to build new fabs in Yongin and Cheongju to respond to the continuously growing demand for memory in the AI era.The company approved a total investment of approximately 54 trillion, on 35.2 trillion won in Yongin "Y2" fab and 19.1 trillion won in the Cheongju "M17" fab, in a board meeting.This decision represents execution of the mid-to-long-term investment strategy announced by the company last June. Under its master plan to invest 600 trillion won in the Yongin Semiconductor Cluster and 100 trillion won to expand its Cheongju production base, SK hynix is currently constructing its first fab in Yongin (Y1). With this latest decision, the company is embarking on the construction of subsequent fabs in both Yongin and Cheongju.According to market research firm Omdia, both DRAM and NAND demand are projected to maintain a compound annual growth rate (CAGR) of 19% from last year through 2030. The company views this growth not as a temporary supercycle, but as a structural transformation in which memory transcends its role as a mere component to become core infrastructure determining AI performance itself.SK hynix stated that in the AI era, technological competitiveness alone is not enough and the ability to supply the required volume at the exact moment customers need it is the ultimate competitive advantage. We reached this investment decision after a thorough review of market demand.Yongin Y2 is the second of four fabs planned sequentially for the Yongin Semiconductor Cluster. It will serve as a DRAM production base spanning a total floor area of 341,000 pyeong (approximately 1,130,000m2). Construction is scheduled to break ground in July next year, targeting the opening of its first cleanroom in June 2029 to produce high-bandwidth memory (HBM) and other next-generation DRAM products. Meanwhile, construction on Y1 is progressing smoothly toward its initial cleanroom opening target of February next year.SK hynix previously set a goal to advance the completion date of the Yongin Semiconductor Cluster by 12 years—from the originally planned 2045 to 2033—to finish constructing all four fabs. The Y2 construction serves as the second phase supporting this accelerated timeline and the investment spans to October 2031 sequentially.The investment amount includes construction costs for "Business Support Building" with administrative and welfare facilities for Y2 personnel, an "Integrated R&D Center" to consolidate product development testing, analysis, and experiments, as well as auxiliary infrastructure1..1Auxiliary infrastructure: Water treatment facilities, utility conduits (underground structures capable of accommodating power lines, telecommunications lines, water/sewer pipes, and thermal supply lines), substations, warehouses, etc.For the Yongin Semiconductor Cluster—sprawling over approximately 1.26 million pyeong(approximately 4,160,000m2) in Wonsam-myeon, Cheoin-gu, Yongin-si, Gyeonggi-do—Phase 1 power and water infrastructure required up through Y2 operation is nearing completion, currently at a 99% progress rate. As fab construction and infrastructure setup have been carried out concurrently, the company plans to proceed with the Y2 construction according to schedule.In the NAND market, demand is surging rapidly centered on enterprise SSDs driven by the full-scale expansion of AI services. This is further boosted by demand for key-value (KV) cache2 storage in AI inference, with application fields expected to broaden further as Agentic and Physical AI are introduced.2KV Cache: A technique that stores and reuses previously computed Key and Value vectors to minimize inefficient redundant calculations during inference.SK hynix selected Cheongju as its new NAND fab base because it offers the fastest fab construction timeline. The Cheongju Campus already houses the M11, M12, and M15 fabs, enabling efficient production linked to existing operations on sites equipped with substantial pre-established power and water infrastructure. Cheongju M17 will be built across a total area of 206,000 pyeong(approximately 680,000m2), breaking ground in February next year with plans to open its first cleanroom in December 2028. The investment period runs through April 2031 according to the master plan.SK hynix plans to proactively secure production infrastructure based on mid-to-long-term demand discussed with customers, while expanding actual production capacity in alignment with the timing of customer needs. Fabs will be constructed according to the master schedule, whereas cleanroom expansions and equipment installation will take place sequentially in line with demand trends to maximize capital efficiency.The company expects this investment to secure future growth foundations while strengthening the competitiveness of the domestic semiconductor ecosystem and boosting local economies. The large-scale simultaneous investments in Yongin and Cheongju are anticipated to expand joint growth opportunities for supply chain partners, generate employment, and revitalize local commercial districts, thereby contributing to the sustainable growth of the national economy.An SK hynix official stated that "This investment is a decision made to seize opportunities in line with the market's growth speed. By proactively securing production capabilities, we aim to establish ourselves as a key partner in AI infrastructure, contributing to the stability of the global AI semiconductor supply chain."SK hynix's Cheongju M17 fab.Credit: SK hynix

As global healthcare systems evolve, preventive medicine and digital health technologies are becoming key drivers of medical innovation. Aging populations, rising healthcare costs, and increasing chronic diseases are accelerating the transition from treatment-oriented care toward preventive, personalized, and data-driven health management.Within this transformation, Traditional Chinese Medicine (TCM) is being re-examined beyond its historical and cultural role. Increasingly, TCM is discussed in the context of systems-based healthcare, lifestyle regulation, and long-term health management. Its emphasis on prevention, adaptation, and holistic regulation reflects growing global interest in healthcare models that focus on maintaining balance and improving overall well-being.TCM has traditionally emphasized the dynamic relationship between human health and environmental changes. Practices such as seasonal adaptation, sleep regulation, dietary management, and stress balance share conceptual similarities with modern healthcare research in areas including circadian rhythms, lifestyle medicine, and preventive care.Meanwhile, advances in digital technologies are reshaping healthcare delivery. Wearable devices, mobile health platforms, and artificial intelligence (AI)-based analytics now enable continuous monitoring of physiological indicators, including heart rate variability, sleep patterns, activity levels, and stress-related signals. These technologies create new opportunities to connect traditional health concepts with modern data-driven healthcare systems.The integration of TCM with digital innovation has become an emerging interdisciplinary field. AI-assisted diagnosis, wearable health monitoring, smart herbal medicine production, digital supply chains, and biotechnology applications are opening new pathways for the modernization of traditional medicine.This article series explores the evolving role of TCM in modern healthcare, covering preventive health, lifestyle management, wearable technologies, AI applications, herbal biotechnology, smart agriculture, and the globalization of traditional medicine.Taiwan’s development in biotechnology, information technology, precision agriculture, and healthcare innovation provides a unique foundation for advancing this integration. Emerging research in plant-derived biomaterials, intelligent cultivation systems, and herbal medicine applications demonstrates the potential of combining traditional knowledge with modern science and engineering.The modernization of TCM does not mean replacing traditional practices with technology. Instead, it represents a process of reinterpretation—using scientific validation and digital tools to enhance understanding, application, and global communication of traditional healthcare concepts.Challenges remain, including standardization, clinical validation, regulatory frameworks, and data integration. However, as healthcare continues to move toward predictive, personalized, and continuously monitored models, TCM may contribute valuable perspectives on preventive care, holistic health management, and system-oriented healthcare thinking.The convergence of traditional medicine and digital innovation will continue to shape new possibilities for the future of global healthcare.

SK hynix Inc. (or "the company", www.skhynix.com) announced today in collaboration with Sandisk that it has unveiled the first standard specifications for High Bandwidth Flash (HBF), a next-generation storage technology.The announcement coincides with the opening of 'FMS (Future of Memory and Storage) 2026,' held at the Santa Clara Convention Center in California from August 4 to 6 (local time). The company is set to present HBF as a key technology to overcome memory bottlenecks in the AI era through keynote speeches and panel discussions during the event.HBF technology is a new memory layer between HBM and SSDs. It enables high-speed data transfer similar to HBM while significantly expanding capacity by leveraging NAND technology. With the expansion of AI inference driving a surge in data volumes to process, HBF is gaining attention as a technology that simultaneously resolves bandwidth and capacity scalability challenges.This milestone comes about six months after launching the consortium in February this year, following the initial standardization partnership with Sandisk in August 2025. Capacity specifications cover up to 512GB based on two stack configurations (8-high and 16-high NAND dies). Bandwidth is categorized into three grades (Grade1~3), delivering scalable performance from approximately 0.4TB/s to 3.0TB/s.A key highlight is the interconnect linking HBF technology and processors. HBF technology adopts UCIe, an industry standard connection interface, laying the groundwork to flexibly integrate HBF technology across different processor types, including GPUs and CPUs.The standard also outlines 1. connection interfaces and electrical characteristics, 2. reliability and packaging guidelines for HBF die stack process, 3. software I/O guidelines.The specification was disclosed through the Open Compute Project (OCP), world's largest open data center technology initiative, positioning it as an open standard for the entire industry rather than a proprietary technology.SK hynix plans to leverage this release to expand the adoption of HBF technology in the AI storage market and foster the surrounding ecosystem. With Google and Tenstorrent currently participating in the HBF consortium, the consortium aims to expand its reach while enhancing technical maturity and market acceptance based on open collaboration.On the opening day of FMS 2026 (August 4, local time), SK hynix Executive Vice President Kim Chun-sung (Head of Solution Development) and Vice President Kang Uk-song (Head of Next Generation Product Planning) will deliver a joint keynote address, titled 'Orchestrating Efficient AI Infrastructure through Tiered Memory in the Era of Agentic AI.'As Agentic AI rapidly commercializes, the volume of data to process is surging alongside growing demands for higher speed and efficiency. Recognizing that a single memory type cannot address these complex challenges, both speakers will present the necessity and future direction of a next-generation architecture based on 'Tiered Memory' a framework that connects and optimizes diverse memory types into a unified system.On August 6, SK hynix Vice President Lim Eui-cheol (Head of Solution AT), Sandisk Vice President Rajeev Nagabhirava and Google DeepMind Senior Staff Engineer Xiaoyu Ma will join a panel discussion titled 'Breaking the Memory Wall with High Bandwidth Flash.' Bringing together key leaders across memory, storage and AI, the session will examine fundamental shifts in memory architecture across AI infrastructure and highlight the potential and role of HBF as a transformative solution.Furthermore, SK hynix will host an exhibition booth throughout FMS 2026, featuring a Partnership Zone, a Next-Generation Tech Zone and Tech Sessions.Notably, the company will publicly reveal for the first time its tenth-generation (V10) 375-layer 4D NAND wafer and products, which are currently under development. The 375-layer 4D NAND improves performance per watt by 2.5 times compared to the previous generation, making it optimized for AI infrastructure environments like data centers that demand high power efficiency and performance. The company plans to initiate mass production of high-performance, high capacity eSSDs based on the 375-layer 4D NAND early next year to reinforce its leadership in the AI NAND market.SK hynix will also display a versatile product lineup spanning mobile, PC, automotive and robotics, showcasing the company's competitive edge in memory technology and its collaborative achievements with customers in the AI era."With the rapid spread of AI applications, we are at a point where overall data processing structures must be redesigned," said SK hynix Executive Vice President and Head of Solution Development Kim Chun-sung, adding, "Through HBF, SK hynix will expand the boundaries between memory and storage and contribute to building new architectures that enhance overall system efficiency."SK hynix exhibition booth at FMS 2026. SK hynix

Montage Technology today announced the industry's first trial production of its CXL 3.2 Memory eXpander Controller (MXC) chip, designed to address escalating demands for memory expansion and resource pooling in AI, cloud computing, and data center environments. Leveraging CXL technology, the MXC chip enables customers to build memory infrastructure with higher capacity, improved resource utilization, and greater flexibility.The CXL 3.2 MXC complies with CXL Type 3 specifications, including both CXL.mem and CXL.io protocols. It is designed with PCIe 6.x and CXL 3.2 protocol support, delivering data transfer rates of up to 64？GT/s. The chip integrates dual DDR5 memory controllers that support up to 8000？MT/s DDR5 memory. By converting host-side CXL memory requests into DDR commands in real time, it enables efficient data exchange between the host and backend memory, effectively breaking through the memory capacity limits of traditional servers.Additionally, the chip integrates PCIe 6.x PHY, DDR5 PHY, dual RISC-V processor subsystems, and a comprehensive set of management interfaces. It supports multiple CXL memory expansion form factors, including PCIe AIC cards and EDSFF modules, providing critical support for emerging memory applications such as memory expansion, pooling, and tiered memory architectures."The trial production of the CXL 3.2 MXC chip marks an important milestone in Montage Technology's pursuit of CXL innovation and commercialization," said Stephen Tai, President at Montage Technology. "As memory demands continue to surge in the AI era, we are providing our customers with high-bandwidth, large-capacity, and highly reliable memory expansion solutions, accelerating the large-scale adoption of CXL in data center and AI infrastructure."In addition to the chip, Montage Technology provides a complete software development kit (SDK) along with analysis and testing tools to help customers accelerate product development, compatibility validation, and mass production. The CXL 3.2 MXC has already been integrated into next-generation CXL products by leading memory module manufacturers, including Samsung and SK hynix, with initial validation successfully completed. The solution is designed to align with leading server platforms, including Intel Xeon and AMD EPYC, to ensure broad interoperability and optimal performance.Customer and Partner Feedback:Jangseok Choi, VP of Memory Product Planning at Samsung Electronics stated: "The combination of CXL 3.2 MXC with DDR5 memory technology offers data center customers a solution that balances performance and capacity. Our collaboration validates the value of CXL in increasing system memory capacity and resource utilization, and provides additional options for next-generation AI infrastructure."Uksong Kang, Head of Next Gen Product Planning&Std at SK hynix noted: "With the rapid adoption of large language models and generative AI, memory has become a critical factor in system performance. Montage Technology's MXC product demonstrates strong potential for supporting high-capacity memory expansion and resource sharing. We look forward to deeper collaboration in ecosystem validation and product innovation."Dr. Debendra Das Sharma, Senior Fellow and Chief I/O Architect at Intel remarked: "AI, next-gen cloud systems, and today's industry economics are reshaping server memory architecture and driving demand for CXL. Montage Technology's CXL 3.2 MXC demonstrates how the maturing CXL ecosystem delivers protocol support, compatibility, and performance, helping to unlock the memory expansion capabilities of next-generation Intel Xeon platforms."Amit Goel, corporate vice president, Compute and Enterprise AI Platform Solutions Engineering, AMD added: "AI and data center workloads are driving continuous evolution of system architecture, making memory a key factor in performance and scalability. We look forward to our continued collaboration with Montage Technology on CXL technologies to deliver a foundation for building more flexible and efficient memory architectures."Upcoming Events:Montage Technology will showcase its CXL 3.2 MXC solutions at the CXL DevCon on August 3, 2026, at the Santa Clara Marriott, and at the FMS (Future of Memory and Storage) exhibition from August 4–6, 2026, at the Santa Clara Convention Center (Booth #845), both in Santa Clara, USA. We warmly invite our customers, industry peers, and partners to visit our booth for in-depth exchanges on industry trends and potential collaboration opportunities.Montage Technology Announces Industry-First Trial Production of CXL 3.2 MXC Chip. Credit: Montage Technology