Advanced Micro Devices (AMD) sees the opportunity for growth in a wave of digital gaming solutions ranging from gaming machines in casinos, amusement with prize (AWP), as well as video arcades in recreational facilities, Japan's Pachinko and Pachislo segment, and video lottery terminals (VLT) worldwide.AMD uses highly integrated, low-power consumption, and powerful parallel embedded computing solutions as well as Eyefinity multi-monitor display technologies to provide optimal solutions for emerging gaming platforms.AMD embedded solutions drive gaming machine innovationsAccording to Kevin Tanguay, Senior Manager of AMD Embedded Solutions, Digital Gaming, various categories of gaming machines commonly are seen in the gaming industry:- Casino machines; casinos often have dozens or even hundreds of gaming machines that offer Pachinko, slot, poker, baccarat, and other games- AWP gaming machines are often found in bars, clubs, coffee shops, small gambling establishments, and are quite popular in Europe- VLT machines connect players to the back-end network of betting agencies, and the size of prizes depend on the number of people betting- Arcade machines with 3D graphics capabilities, surround sound, and tactile feedback control devices, often are seen in department stores or entertainment facilities- Japan's unique Pachinko and Pachislot segment includes prize winning probabilities based on a random number generator (RNG).AMD's Embedded APUs are equipped with AMD Dual Graphics and Eyefinity technologies. The mainstream G-Series APU is well suited for the design of VLTs. The performance grade R-Series is well suited for VLTs as well as Pachinko and Pachislot machines. The performance grade AMD Embedded R-Series equipped with multi-screen output capabilities can collaborate with independent GPU products and is well suited for VLT, Pachinko and Pachislot, casino, AWP, and arcade gaming machines. AMD's embedded solutions offer a complete and comprehensive range of APU, GPU, CPU and chipset products -- the most advanced PC technology to help drive the embedded market. AMD also offers an exclusive and stable customer support system, a five-year long-term supply guarantee, and an exciting development roadmap for new products.Roadmap for AMD Embedded productsRegarding the scheduling for high performance APU products, supplies for the 2011 FS1 socket design standard "eLlano" APU will last for five years. The 2012 AMD R-Series APUs with Socket FS1r2 slot/pin designs include the 35W quad-core R-464L/2.3 (3.2) GHz, and R-460H / 1.9 (2.8) GHz, as well as the 35W dual-core R-272F / 2.7 (3.2) GHz and R-268D / 2.5 (3.0) GHz. R-Series APUs offer quad-core (R-4xx) or dual-core (R-2xx) configurations, provide DDR3 memory support, have a built-in DirectX 11 GPU, as well as PCIe bus controller, and support AMD Dual Graphics technology. In addition, there are also low-power consumption FP2 BGA flip-chip package versions such as the 25W quad-core R-464L/2.0 (2.8) GHz, 19W quad-core R-452L/1.6 (2.4) GHz, and 17W dual-core R-260H/2.1 (2.6) GHz and R-252F/1.9 (2.4) GHz models. These models are all equipped with A70M or A75 southbridge controller chips. In 2013, AMD will launch an FP2 (BGA) flip-chip packaging R-Series APU with upgraded clock speeds.Taking the high-performance AMD R-Series APU as an example, it has two built-in dual-core, 2MB L2 cache cores, DirectX 11 GPU, and 3x DP/DVI/HDMI/LVDS display interface driver circuits that are connected to the AMD A70M/A75 southbridge controller chip with an X4 UMI bus. The built-in GPU specifications for the R-Series APU support H.264 HD (1080p@60fps) as well as VC and DivX decoding standards; its built-in DDR3 memory controller supports DDR3-1600. 4K by 2K resolution display output is supported, and it can connect to four external monitors for crossover displays when equipped with a HDCP, 5.4Gb/s link rate interface; and can support a total of 10 parallel display outputs when connected to an external PCIe E6460/E6760 with six DisplayPort(DP) v1.2 interfaces or MXM modules.Compared to Intel's embedded solution, the AMD Embedded R-Series APU provides DirectX 11 hardware acceleration, four full HD screen resolution outputs, support for 4K by 2K@60Hz maximum resolutions, parallel dual graphics card technology (dual graphics), and OpenCL to provide support for fast parallel computing. When the graphics performance of AMD's 35W quad-core R-464L and R-272F, as well as Intel's 45W Core i7-2710QE, 35W Core i5-2520M, and Core i3-2310M platforms are compared using Futuremark 3DMark Vantage v1.1.0 and 3DMark 06 v1.2.0; if the measured performance value of Intel's Core i7-2710QE is standardized at 100%, then the performances of the Core i5-2520M and i3-2310M are 98% and 88%, respectively; and the performance values of AMD's R-464L and AMD R-272F can reach 210% and 142%, respectively, which is equivalent to between 1.4 and 2.1 times the graphics computing performance of the Intel Core i7/5/3-2x00 series.The FS1r2 (PGA) package AMD APUs in conjunction with the A70M/A70 bridge chip allow for the PCB area of the entire system to range in the ballpark of only 1437mm- to 1483mm-squared.On the product roadmap for low-power embedded G-series processors: in 2011, AMD launched FT1 BGA packaged chips without built-in GPUs such as the 18W dual-core T48L/1.4GHz, 18W single-core T30L/1.4GHz, and 5W single-core T24L/1GHz; mid-range single-core with built-in GPU products such as the 18W T52R/1.5GHz, 9W T44R/1.2GHz, and 5.5W T40R/1GHz; as well as the high-end dual-core G-Series with GPU models such as the 18W T56N /1.65GHz, 18W T48N/1.4GHz, 9W T40N/1GHz, and 6.4W T40E/1GHz. In 2012, AMD fully moved towards single-/dual-core built-in GPU solutions such as the 18W dual-core T56E/1.65GHz, 18W dual-core T48E/1.4GHz, and single-core 4.5W T16R/615MHz models.Roadmap for AMD Embedded GPU productsFor discrete embedded GPU products: in 2008, AMD launched the ATI Radeon E2400 embedded GPU consuming less than 20W of power, with 128MB of GDDR3, DirectX 10/OpenGL 2.0/UVD hardware acceleration, and support for RGB/DVI/HDMI/LVDS display interfaces. In 2009, AMD launched the ATI Radeon E4690 GPU consuming less than 30W of power, with 512MB of GDDR3, DirectX 10/OpenGL 2.0/UVD hardware acceleration, and support for RGB/DVI/HDMI/LVDS/DP v1.1 interfaces. In 2011, AMD launched the 20W AMD Radeon E6460 GPU with 512MB of GDDR5, DirectX 11/OpenGL 4.1/UVD3 hardware acceleration, and support for RGB/DVI/HDMI/LVDS/DP v1.1a/1.2 interfaces; as well as the 30W AMD Radeon E6760 GPU with 1GB of GDDR5, DirectX 11/OpenGL 4.1/UVD3 hardware acceleration, AMD Eyefinity technology (capable of six screen outputs), and support for RGB/DVI/HDMI/LVDS/DP v1.1a /1.2 display interfaces.For embedded GPU MXM modules, in 2008, AMD launched the ATI Radeon E2400 MXM 2.1a Type II module consuming less than 25W of power. In 2009, AMD launched the ATI Radeon E4690 MXM 3.0 Type A module consuming less than 35W of power. In 2011, AMD launched the AMD Radeon E6460 MXM 3.0 Type A module consuming 35W of power as well as the ultra-high performance AMD Radeon E6460 MXM 3.0 Type B module consuming less than 110W of power, and backed by a three-year supply period. In 2012, AMD launched ultra-high performance AMD Radeon HD 7970M MXM 3.0 Type B modules. The ATI Radeon E2400 MXM module will officially reach EOL in July of 2013 after its five-year supply period.Regarding AMD's embedded PCle add-in card range: for the less than 25W power consumption mainstream segment, AMD launched ATI Radeon E2400 PCIe add-in cards with dual DVI-I and a passive heat-sink design in 2010, , as well as AMD Radeon E6460 PCIe add-in cards with dual-DVI or quad-mDP, and quad-DVI with heat-pipe designs in 2011. For the less than 35W power consumption segment, AMD launched ATI Radeon E4690 PCIe add-in cards with dual-link DVI-I connectors and cooling fan or heat-pipe designs in 2009, as well as AMD Radeon E6760 PCIe add-in cards with dual-DVI and six mDP or six DVI connectors with heat-sink or heat-pipe designs in 2011. For the ultra-high performance (<110W) market, AMD launched the AMD Radeon HD 5770 and AMD Radeon HD 6850 PCIe add-in cards, as well as the AMD Radeon HD 7850M in 2012 with a three-year product supply guarantee.Specification differences between the AMD Radeon E6460 and E6760 are that the former has a package size of 33mm by 33mm with 20W power consumption, 160 shaders, and 64-bit 25.6GB/s bandwidth 512MB GDDR5; and the latter is a 37.5mm by 37.5mm multi-chip-module (MCM) with 35W power consumption, 480 shaders; and 128-bit 51.2GB/s bandwidth 1GB GDDR5. In 3DMark Vantage graphics performance benchmarks, the AMD Radeon E6460 scores 2195 and supports four-screen outputs, and AMD Radeon E6760 scores 5870 and supports six-screen outputs. Both the AMD Radeon E6460 and E6760 have MXM 3.0 Type A module and PCIe add-in card versions.APU acceleration technology activated by external GPU Dual Graphics processingTanguay said because AMD APUs are equipped with AMD Dual Graphics technology, as long as they work in conjunction with the AMD GPU add-in cards or modules, parallel computing between the APU's built-in GPU and the add-in cards can be activated. Test results indicate that the T56N APU with an E6460 GPU module/add-in card can enhance performance by 77%, R-Series APUs with an E6460 GPU module/add-in card can see performance enhanced by 40%, and the T56N APU with an E6760 GPU module/add-in card can achieve performance gains of 16%.Regarding the low-power consumption G-Series APUs; if the T40E has a performance benchmark of 1.0, then the relative performance of the T48E is 1.1, the T52R 1.33, T56N 1.67, and the T56N with an E6460 GPU can be enhanced to 2.4. As for embedded GPU modules; if the previous generation E2400 GPU has a performance benchmark of 1.0, then the E6460 GPU can reach 1.94, the previous generation E4690 can reach 2.88, and the E6760 can reach 3.94.Tanguay summarized that with its innovative silicon technology, AMD is able to build an ecosystem for its customers. AMD provides a complete series of APU and GPU chips with functionality, flexibility, and energy efficiency for gaming manufacturers. AMD's digital gaming solutions can take advantage of real-time 3D graphics technology to provide HD and multimedia video, and realize the ultimate in gaming and entertainment. At present, more than 120 platform solution providers as well as motherboard and peripheral suppliers worldwide have chosen AMD's embedded products to assist the gaming industry in developing lower TCO gaming machines. AMD's embedded chip business group can provide long-term and stable product supplies, strengthening the businesses of gaming manufacturers, and making it a trusted partner for the gaming industry.Kevin Tanguay, Senior Manager of AMD Embedded Solutions, Digital Gaming

In addition to introducing a full range of embedded application products that meet the OpenCL specification, US-based Advanced Micro Devices (AMD) has collaborated with its industrial partners to develop multiple application procedures, code samples, and software libraries that can exert the parallel computing performances of the heterogeneous multicore architecture APUs and GPUs using the Accelerated Parallel Processing (APP) technology from AMD.AMD constructs the heterogeneous multicore acceleration processor architectureKelly Gillilan, embedded solutions product marketing manager of AMD, stated that today's multicore processors are divided into homogeneous and heterogeneous models, and the latter is composed by two or more different types of cores. The accelerated processing unit (APU) architecture concept proposed by AMD has the heterogeneous multicore comprised of the x86 CPU that is known for its memory read/write capabilities and the multi-floating point/3D graphics computing GPU core. In June 2012, AMD, ARM, Imagination, MediaTek, Texas Instruments and Qualcomm established in the Heterogeneous System Architecture (HAS) Foundation to collaborate and promote the standardization of heterogeneous multicore.The first open source and free universal acceleration application programming interface (API) specification in the industry was the Open Computing Language (OpenCL) developed by the Khronos Group. AMD is the early incorporator and supporter of OpenCL and has created numerous application procedures with its technical partners, code samples, and software libraries through AMD's APP technology; which enables OpenCL to exert the full acceleration power of parallel computing in heterogeneous multicore systems.AMD offers a full series of OpenCL-compatible heterogeneous parallel processing application products ranging from the low power G-Series APU that is designed to consume only 4.5W to 18W of power with the maximum parallel computing performance of 80GFLOPs, to the high-performance R-Series designed to consume 17W to 35W of power and provide 500GFLOPs of parallel computing performance. The AMD Radeon GPU series, including the AMD Radeon E6460 GPU, adopts a BGA package and the MXM module or PCIe add-on card format, and is designed with a power consumption rate of 20W in conjunction with the 25GB/s bandwidth GDDR5 memory to produce a floating-point performance of 192GFLOPs. The E6760 GPU adopts a BGA package and the MXM module or PCIe add-on card format, and is designed with a power consumption rate of 35W in conjunction with 51GB/s bandwidth GDDR5 memory to produce a floating-point performances of 576GFLOPs. The E6970 GPU adopts the MXM module, and is designed with the power consumption rate of 95W in conjunction with 115GB/s bandwidth GDDR5 memory to produce a floating-point performance of 1.3 TFLOPs.The Basic Concept and writing style of OpenCLGillilan pointed out that OpenCL is different from the Open Graphic Language (OpenGL) used for image processing in the past, in that OpenCL incorporates GPUs for computing purposes. The platform defined by OpenCL means that the system's host (generally the CPU) framework shares resources with applications as well as a collection of multiple execution program kernels on devices. Each computer device receives from one to many compute units, and inside each unit there are from one to many basic processing elements.Take the array loop model of the C language as an example, the traditional code may be int i; for (i=0;i<n;i++) c[i]=a[i]*b[i]. However, when incorporated into OpenCL, the "Kernel" keyword must be added to the beginning and end of the code, and the code itself becomes int id = get_global_id (0); c[id]=a[id]*b[id]. That is, the array is broken into 1 to n pieces, and the system configures the n cores to perform the parallel computing. OpenCL would determine the front and back mapping relationships among the allocated kernels. After data from each Kernel is completed and outputted, the system would wait until all other core data is outputted and assembled before proceeding to the next step.Memory in OpenCL is divided into four major blocks - Global Memory is the read-only memory that can be reached by each computer device and internal compute unit; Global/Constant Memory DataCache is used by the OpenCL library; each computer device (meaning a CPU or GPU) has its own local memory; and the most basic internal compute unit of each compute unit has its own private memory.The OpenCL program writing model is also divided into: 1. Host executed codes; 2. Header, as each parallel computing code fragment allocated must be defined by a header and a declaration; and 3. Kernels, which are assigned and allocated by the OpenCL function to each part of the core.AMD recommended the industry to: 1. Create a development environment that can run under both Windows and Linux; 2. Download the latest AMD Catalyst software driver; 3. Download the AMD APP SDK development kit 2 (Microsoft Window 7 and later versions supported); 4. Perform the internal SDK sample programs; 5. Attempt to establish and execute a program sample; 6. Start writing the program and modify the program samples that are transferred into the SDK; and 7. Establish a unique code as well as write them into the hardware platform, and run it through a simulator or in a debug environment.AMD has also established the OpenCL Zone dedicated webpage where developers can download the startup training manual documents, APP SDK Development Kit, etc., for free. Other industry partners include the Sage Probe/EDK hardware debug package from Sage Electronic Engineering and the multicore coding, algorithm transplantation, and debug consultation services offered by Texas Multicore Technologies (TMT).Viosoft uses OpenCL to accelerate the network packet processing applicationsNext, Charles Chiou, the Taiwan country manager of Viosoft, explained the OpenCL development tools and resources, and provided samples for network packet processing under the AMD APU platform. Chiou believed that the traditional CPU and GPU has to go through the slower PCI/PCIe bus communication, which forms a packet transmission bottleneck and has a higher power consumption cost. An APU has more than 80 built-in Radeon graphics processing units for parallel computing, which can be applied to visual computing and Internet transaction security codecs. APU outperforms the traditional CPU with independent GPUs in both the unit/watt performances as well as system volume size, and can handle the needs of the next-generation network packet processing applications.Chiou used Vodafone (Australia) as an example, which offers free packets (such as those on Facebook), discounts through other Internet ISP networking, advertising content for viewing packets, and zero rate Internet shops (where the advertising suppliers are responsible for the costs). Traditional networking equipment that monitors only packet traffic such as routers, firewalls, NAT internet Redirection and VPN virtual private network devices cannot handle these types of network packet billing mechanisms that are based on the different content types and sources.Viosoft is currently collaborating with AMD to implement the Teranium project plan, which uses OpenCL plus GPUs to accelerate packet processing. The OpenCL is controlled by the x86 architecture that can monitor the centralized data of basic network packets, focus on the various packets of the Internet and distinguish the timing and user-generated content, and focus on audience-specific advertising or promotional activities while filtering junk mail and preventing attacks by viruses or malicious network packets.Chiou indicated that the current mainstream network equipment is Deep Content Inspection. However, to meet the demands of zero-rate and pay by the sender side network packets with certain requirements, the network equipment must evolve to have the systemic content processing technology that uses the software definition method to monitor and filter a wide range of packets. After Viosoft has incorporated the OpenCL optimized network packet program into the APU chip of a 1U rack-mounted dual AMD APU chip system with dual 10Gbit LAN interface, the APU chip can fully exert the offload engine function and increase the IP packet forwarding performance by up to 50% (5Gbps).Viosoft is currently collaborating with AMD to implement the Teranium project plan, which is the optimized 4x10Gbit (4-port) network interface driver with the deep-packet inspection extensible framework that can bypass the TCP/IP software stack layer of the Linux core. Their research found that it is not enough to drop the load of the CPU. The correct strategy is to transfer a large amount of packets from the CPU to the GPU for parallel processing. Of course, like the device driver code, the data packet scheduling and the panel controlling codes must still be executed within the CPU. Meanwhile, researchers can endeavor to determine the best method to resolve problems such as the number of copies made in the memory, CPU/GPU communication bottlenecks, and load scheduling.OpenCL parallel acceleration computing can enhance performance from tens to hundreds of timesChiou described the acceleration performance made by the actual OpenCL by stating that a CPU with an external AMD Radeon 5450 HD GPU card is used in conjunction with the Persimmon board with an Embedded G-Series APU. Under OpenCL, the APP acceleration enables the parallel computing DES coding, DES decoding, AES coding, and AES decoding for the CPU and GPU. For the DES coding part, Radeon HD 5450 increased from 0.25 to 8.0 and G-Series APU significantly increased from 0.57 to 52.67. For the DES decoding, the Radeon HD 5450 increased from 0.25 to 5.5 and the G-Series APU significantly increased from 0.62 to 52.25. For the AES coding, the Radeon HD 5450 increased from 0.11 to 13.4 and the G-Series APU significantly increased from 0.85 to 59. For the AES decoding part, the Radeon HD 5450 increased from 0.4 to 9 and the G-Series APU significantly increased from 0.62 to 72.42. Overall, the acceleration can improve performances from 22 to 120 times.Finally, Chiou introduced the Integrated Development Environment (IDE) kit developed by Viosoft for the AMD APU platform and downstream developers. The IDE kit is comprised of GNU and Linux Embedded Editions. Viosoft also developed the ARRIBA remote cross-platform virtual debugging technique. The client embedded Linux AMD APU platform is located in Atlanta but can be remotely controlled by engineers at Austin, Texas. After running the VMON virtual device, the engineers' computers can communicate with the AMD APU platforms on the other end even while using a Windows or Linux operating system, and then list the internal modules and code snippets to perform single-step executions and debugging steps.Kelly Gillilan, embedded solutions product marketing manager of AMDCharles Chiou, the Taiwan country manager of Viosoft

Advanced Micro Devices (AMD) has launched a full range of OpenCL-compatible heterogeneous parallel processing products, including traditional x86 CPU, GPU and integrated APU chips, as well as embedded GPU chips/MXM modules and add-on cards, etc.Not only has AMD won acclaim with its AMD Turbo CORE, AMD Eyefinity, and AMD Dual Graphics technologies, AMD is also committed to establishing a comprehensive heterogeneous multi-core industrial alliance and ecosystem with the midstream and downstream hardware and software industry sectors to bring embedded systems into the new realm of heterogeneous parallel processing.Careful observation of the embedded market and continued R&D investmentsArun Iyengar, corporate vice president and general manager of the AMD Embedded Solutions Group, indicated that the scope of applications for the embedded market is very broad. The sales cycle for the entire product line is considerably longer than in other markets. During the early stages of the cycle, suppliers would have 3 months to send samples and selections to customers. After the design is adopted (design win) the SI certification stage is approximately 12 to 18 months. Finally, moving a product from engineering prototype to mass production for the customers would stretch for another 36 to 60 months. This entire process could take up to a decade for defense military institutions.The embedded market is more focused on the optimal heat dissipation rate by adopting low power consumption, no cooling fan, higher functionality integration, and more compact designs to create the smallest sized products with optimal energy efficiency in order to lower the total cost of ownership (TCO). The customers hope suppliers can fully understand its product strengths and weaknesses, provide solutions, and tailor the various solutions to respond to the specific needs of the market.Iyengar indicated that AMD is carefully observing the development of the entire embedded market and continues to invest in its R&D. Since June of 2012, AMD's Embedded Solutions Division has been organized into an independent group. In October of 2012, CEO Rory Read indicated that the embedded market has become the group's rapid-growing emerging business; and 2013 is regarded as the first year for AMD embedded solutions.AMD, a pioneer in the embedded market for many yearsIyengar stressed that AMD has been a pioneer in the embedded market for numerous years. From the Am386 and Am486 processors in 1991, the Am5x86 in 1995; the Elan SC520 in 1999; the acquisition of Alchemy Semiconductor and National Semiconductor (NS) by the AMD Geode processor business group between 2002 and 2003; the addition of the 64-bit AMD Opteron, AMD Athlon, AMD Turion, and Mobile AMD Sempron processors into the embedded market; and the ATI Radeon E2400 GPU launched in 2008, and only reached EOL this July. In 2009, AMD launched the ATI Radeon E4690 GPU with 2D and 3D multimedia graphics performance and multi-screen output capacity that is suitable for a wide variety of embedded applications in gaming consoles, consumer electronic products, digital billboards, and industrial control boards, as well as for applications in the medical, defense, and aerospace fields. AMD also introduced the BGA flip chip packaging that is suitable for small size ASB1 processor systems.AMD released the Embedded G-Series APU platform in 2011, and launched the Embedded R-Series APU platform that focuses on high-end graphic performance in 2012. In 2013, AMD will launch embedded applications that are integrated with high-performance graphics and computing performances as well as the SoC silicon chip program that can connect a wide range of I/O peripherals together as one.AMD will continue to provide product supply, open-source operating system support, drivers, software libraries, development platforms, and technical support for its embedded market products for 5 to 7 years. AMD will also provide diverse product selection from the initial silicon circuit design stage to the engineering sample stage, and will eventually link and intimately collaborate with the existing industrial ecosystem.Market is at a heterogeneous multicore emerging stageIyengar used a three-stage CPU evolution schematic diagram to illustrate his point. The single-core CPU has long since reached its development bottleneck. The homogenous system would also reach the power, parallel oriented software, and performance bottlenecks as the number of cores has increased to a number that cannot continue to be sustained. The heterogeneous system is at a burgeoning stage. The data parallel mechanism enabled by energy efficient GPUs can ensure the continued improvement of performance, although in extending performance, the traditional programming models must be subverted and changed.Iyengar also mentioned the developmental history from the early single-core microprocessors to the homogenous multi-core systems, and the advent of the heterogeneous multi-core system. The AMD APU combines the serial data processing of the traditional CPU with the parallel data processing of the traditional AMD Radeon GPU into one. Products like the AMD Embedded G-Series APU (G-T16R APU) have the average power consumption rate of only 2.3W and an I/O controller chip that consumes less than 1W; it is suitable for extremely small and convenient-to-carry embedded mobile devices without a cooling fan. The AMD Embedded R-series APU comprises the quad-core x86 core and the AMD Radeon 7000 GPU core with 384 parallel arithmetic units, which provide high performance that can rival independent GPU graphics performance with DirectX 11 hardware acceleration specifications and can use the OpenCL and DirectCompute software to provide program solutions to enhance the performance of embedded platform computing to another level.Embedded product line and key technologies of AMDThe AMD embedded product line is divided into different series. The R-Series APU provides appropriate performance, energy efficiency, and above high definition (HD) visual experiences. The G-Series APU emphasizes low power consumption as well as unprecedented GPU integration, and is suitable for mini and fanless system designs. In addition, the AMD Radeon GPU provides amplified 3D and multimedia performance specifically for embedded systems, and its product delivery cycle is ensured for up to five years.Iyengar introduced the first key technology of the AMD APU, the AMD Turbo Core. Taking the AMD R-464L as an example, the x86 core clocks at 2,300 MHz and its GPU clocks at 496MHz. Under the general load balanced state of the x86 core and its GPU, each clock remains unchanged. When the system enters the multi-threaded parallel processing state, the clock of the x86 core would dynamically increase by a maximum of 39% (up to 3,200 MHz), but the clock of the GPU remained unchanged. When implementing programs that emphasize 3D graphic processing, the clock of the x86 core remained at 2,300MHz, but the clock of its GPU would dynamically increase by a maximum of 38% (685MHz). Depending on the needs of the load, the APU can provide bidirectional and dynamic clock adjustments for the GPU and the x86 core.The other key technology is the AMD Eyefinity technology. The AMD R-series APU can provide external connections and has parallel display ports for four monitors. When connected to an external PCIe add-on graphics card with six DisplayPort (DP) v1.2 interfaces, the system can expand its access capacityto up to ten monitors. The general embedded systems designs based on the Intel CPU can only enable either the internal GPU or the external Radeon GPU chip even with the additional add-on standalone GPU chip. However, the AMD APU is equipped with AMD Dual Graphics technology that enables the internal Radeon7000 GPU core to operate in parallel with the external Radeon E6460/E6760 GPU chip to further compact and enhance the 3D and multimedia graphics computing performance.Iyengar indicated that the AMD G- and R-series APUs can be applied to digital billboards, casino gaming machines, IP-TVs, x86 set-top boxes, medical applications, POS terminals and phone booth kiosks/automatic ticketing systems, thin clients, video conferencing, human machine interfaces (HMI), and industrial control applications, as well as communications machines/infrastructures.Unifying the industry to form the heterogeneous system architecture (HSA) foundation for the promotion of the parallel processing technologyIyengar stated that parallel computing can be applied to video and image processing such as machine recognition, medical imaging, intelligent billboards, and video surveillance; digital signal processing such as telecommunications and national defense; network traffic packet processing; and green high performance computer (HPC) applications. AMD offers a full series of OpenCL-compatible heterogeneous parallel processing application products ranging from the low power consumption G-Series APU that is designed to consume only 4.5W to 18W of power with 80GFLOPs of maximum parallel computing performance to the high-performance R-Series designed to consume 17W to 35W of power and provide 500GFLOPs of parallel computing performance.The AMD Radeon GPU series, including the AMD Radeon E6460 GPU, adopts a BGA package and the MXM module or the PCIe add-on card format, and is designed with a power consumption rate of 20W in conjunction with the 25GB/s bandwidth GDDR5 memory in order to deliver its 192GFLOPs floating-point performance. The E6760 GPU adopts a BGA package, the MXM module, or the PCIe add-on card formats; and is designed with the power consumption rate of 35W in conjunction with the 51GB/s bandwidth GDDR5 memory in order to deliver its 576GFLOPs floating-point performance. The E6970GPU adopts the MXM module, and is designed with a power consumption rate of 95W in conjunction with the 115GB/s bandwidth GDDR5 memory in order to deliver its 1.3 TFLOPs floating-point performance.In June 2012, AMD brought together ARM, Imagination, MediaTek, Texas Instruments (TI), Samsung, and Qualcomm to form the nonprofit HSA Foundation in order to establish a complete industrial chain from the Silicon Intellectual Property (Silicon IP) to the software developers and to promote the standardization of the heterogeneous system architecture.AMD has unified many of its industry partners such as Sage Electronic Engineering, LLC.; ALT Software; CORELIS; Core Avionics & Industrial, LLC.; Express Logic; ELTAN; Green Hills Software; Texas Multicore Technologies, Inc. (TMT); Fluendo; Viosoft; etc.; to cooperate in finding a solution that can ensure prompt R&D and system integration for the OEM manufacturers. For example, Gizmo, the AMD Embedded G-Series APU based small development platform, has the circuit board area of only 4x4 inches and provides I/O peripheral interfaces such as USB ports, 5.1 channel connectors, VGA ports, PS/2 keyboard and mouse ports, and SATA ports. The Gizmo development platform was originally developed under collaboration by AMD, Sage, Viosoft, and Texas Multicore; provides Windows, Linux, and RTOS operating system and associated drivers; and its back-end software and technical support is provided by the nonprofit technology community GizmoSphere.Iyengar also indicated that AMD and ARM are long-term and strategic cooperation partners with close and well established working relationships. AMD will add the 64-bit ARM authorized ARM processor chips into its production line, and continue to supply the x86 architecture chips, while increasing investments in software development. He concluded that AMD will continue to expand investments in the embedded market, as well as provide superior products that focus on key market applications while satisfying the needs of the consumers and the market.Arun Iyengar, corporate vice president and general manager of the AMD Embedded Solutions Group

Due to huge industrial ecology as well as hardware and software support, NXP has introduced the 100% focused 32-bit ARM architecture low power consumption (LPC) series MicroController Unit (MCU) with low pin count, low power consumption, and low cost simplified system design that can be used for intelligent industrial control applications such as outdoor lighting equipment, factory automation, equipment HMI human interface devices, elevator/lift controls, touch applications, smart grid/ammeter, and smart indoor lighting.NXP also provides a complete set of development tools, evaluation boards and software libraries, abundant third-party software development/debugging tools, and community support to enable the rapid develop a variety of intelligent industrial applications by the industry….Intelligent industrial control applications that are 100% focused on ARM architectureJeff Liu, technical marketing manager of NXP Semiconductors (NXP) in Taiwan, indicated that NXP's LPC series MCU is fully focused on industrial control/embedded applications, which is 100% dedicated to the 32-bit ARM processors. The MCU adopts an extendable 32-bit ARM core architecture and enjoys software/hardware intellectual property (IP) reusability/portability made possible by the extensive ARM industry ecology, which enables a fast-growing industrial ecosystem with community and technical support. NXP provides the LPCXpresso development tools, free open source codes, and third-party vendor support. The award-winning innovation enables connectivity, flexibility, integration, packaging, power efficiency, ease of use, and long service life.The Cortex M0 ARM was launched for low-power embedded applications, and the even-lower power consuming Cortex M0+ core was further introduced during late 2012. Focusing on the alternative market for the 8/16bit MCU, NXP has launched LPC800, LPC1100 (Cortex M0) that have 110 μAmp/MHz low-power consumption running in active mode; adopt TSSOP, SO, and DIP packages; and provide the LPC1100 designed ultra-small WL CSP module package (2mm x 2mm) that make these models ideal for active cable applications. NXP has also introduced a comprehensive series of products for the USB market segment ranging from the low cost LPC1100 and LPC1300 to LPC1700, LPC1800, and LPC4300. The USB driver codes for these products can be built-in into the internal ROM and free software and technical support are also available. The LCD Controller supports 1024x768 resolution and 24bbp color to provide a complete product for the market segment, such as the high-end LPC1700, LPC1800, and LPC4300. Free LCD software libraries are also available. NXP has introduced the fastest 180MHz Cortex-M3, 204MHz Cortex-M4 microprocessor products to meet the performance demands of embedded applications. The LPC4300 adopts the Coretex-M4 plus Cortex-M0 dual-core unique design.Under the present industrial interconnection scheme, outdoor lights/lighting equipment, smart meters, and indoor elevators are connected to the control room via cloud control or a wired method; automated factory machines and equipment are also connected to the control room via the PLC programmable logic control gate through Ethernet; and household automation includes using Zigbee to provide wireless controlled intelligent lighting. These embedded applications include point-of-sale (POS) devices, PLC controller, human machine interface (HMI) on machines, car alarms, etc.The LPC178x/1800/4300 series PLC controllers specifically designed for HMI applications have the maximum 1024x768 LCD display capacity and maximum 204MHz clock; Ethernet, USB, and UART connectivity; as well as rapid assessment and development kit provided for R&D. The LPC178x/1800 specifically developed for elevator control is equipped with a 7-inch LCD display module, uses CAN Bus to replace the old RS-485 interface, and uses a simple system architecture to reduce design as well as FPGA and BOM meter costs.Touch applications such as the LPC1700 series support device firmware upgrades from USB (USB DFT), provide dual SPI port and high-performance CPU data operations, have low-power consumption, and are certified by the USB specification. Smart grid/smart meter product planning includes the EM773/783 plug meter, LPC122x 1-ph meter, LPC122x entry-level collector, LPC2000/LPC17xx 3-ph meter, LPC18xx/ LPC40xx data collector, and LPC43xx/LPC32xx concentrator applications.The LPC series provide CFL and LED intelligent lighting solutions that allow iPad/iPhones to control lights through switches, touch control capacitive switches, and wireless light sockets. In addition, there is also the TCP/IP to JenNet gateway wired intelligent lighting solution.Blueprint for the LPC series embedded MicroController productsLiu also illustrated NXP's blueprint for the LPC series embedded MCU products. NXP's LPC series controllers have accumulated 10 years of the ARM core R&D experiences and are divided into the entry level LPC Go series, the mainstream LPC Connect series, and the high performance LPC Connect/Turbo and LPC Command series. Their clock frequencies range between 30, 50, 70, 72, 100, 120, 125, 180, and 204 MHz; they have between 8 and 296 pins, and their flash memories range between 4KB to 1MB.LPC Go come in LPC800/1100/1100LV/11E00/131x/210x models; adopts the Cortex M0/M3/ARM7 core architecture; has frequencies ranging between 30, 45, 50, 70, and 72 MHz; has reduced system power consumption and design costs; can replace the 8/16 bit MCU and be rapidly incorporated into the market; and adopts the 8 to 64 pin design as well as the 4KB to 128KB flash memory capacity. Liu indicated that the LPC800 series is further divided into five different models: LPC800M021FN8, LPC811M001FDH16, LPC812M101FDH16, LPC812M101FD20, and LPC812M101FDH20. These models adopt the Cortex M0+ core architecture, 2-stage pipeline, and single-cycle I/O design and can provide 0.93DMIPS/MHz of execution performance.The LPC Connect series LPC11Uxx/LPC11Cxx/11A00/1200/134x/213x/214x also adopt the Cortex M0/M3/ARM7 architecture with a 50/60/72MHz frequency, USB and CAN bus controller or Segment LCD display, connectivity, 20 to 64 pin design, and 16KB to 512KB of flash capacity. Liu indicated that the CAN bus controller equipped LPC11Cxx series is comprised of the LPC11C12, LPC11C14, LPC11C22, and LPC11C24 models; and the non-CAN transceiver LPC11C1x series such as the LPC11C00 with LPC1700 can be used for robotic automation applications in factories. LPC1800 and LPC4300 connected to LPC1700 through a CAN Bus or RS-485 can serve as a programmable logic controller (PLC) application.The high performance LPC ConnectPlus series include LPC407x/408x/1700/2300/2400 models that adopt Cortex M3/M4/ARM7 core architecture with the faster 72/100/120MHz frequency, provide USB plus Ethernet/LCD/CAN bus controller, 80 to 208 pin design, and 32KB to 512KB of flash capacity. Liu mentioned that the LPC177x/8x and LPC407x/8x series in conjunction with an LCD display module can be applied to HMI devices for machine equipment or household automation control devices.Blueprint for LPC dual-core embedded processorThe LPC ConnectTurbo series is comprised of the LPC1800/4300/2900 models. It has the fastest clock frequency combinations of 125/180/204MHz; provides optimal integration options such as HS USB, LCD, CAN with Ethernet and DSP instruction set acceleration; and diverse designs such as 144 to 256 pin numbers and 512KB/768KB/1MB flash memory capacities. These chips can be applied to wireless walkie-talkies, factory/laboratory testing machines, electronic medical equipment, and wireless network base stations/infrastructures.Liu specifically introduced the LPC43xx series comprised of the following 11 models - LPC4312/4313/4315/4317/4322/4323/4327/4333/4337/4353/4357. The entire series adopt the optimal 204MHz Cortex M4+Cortex M0 large and small dual-core design, are equipped with field magnetic oriented control (FOC) required for motor control, and provide features such as circuit and industrial control bus controllers, high-speed SPI flash interface that connects to serial flash in order to accelerate firmware read and execution speeds, state configurable timer, and serial GPIO serialization signal line control.The LPC Command series is comprised of the LPC3100 and LPC3200 models that adopt ARM9 micro core architecture with the clock frequency of up to 266MHz. These models can execute high-end operating systems such as Linux and have 180 and 296 pin number package options as well as the external flash memory (flashless) designs.LPC development engineering suite and third-party products/community supportLiu explained that the first step to develop the NXP LPC MCU for intelligent industrial control applications is to select the optimal software development platform. NXP provides the LPCXpresso integrated development environment (IDE) with the maximum firmware code compilation capacity of 128KB. There are also third party IDEs such as Keil/ARM MDK, Embedded Workbench from IAR, Red Suite from Code_Red, Crossworks from Rowley, TrueStudio from Atollic, and other GNU open source compiler software.The hardware debugger is supported by NXP's LPCLink (on LPCXpresso development board), Segger Company's J-Link, IAR/Signum's I-Jet/JTAGjet, Keil/ARM ULink2, Code Red Company's Red Probe, Hitex Company's Tantino, and Lauterbach Company's Trace32.The evaluation/development board is comprised of NXP's LPCXpresso board and built-in LPCLink debug cable/kit combined with the previously mentioned LPCXpresso IDE to provide the lowest embedded engineering assessment costs/development platform for the clients. At present, the LPCXpresso forum has more than 1,000 registered members. In addition, NXP also provides the mbed rapid engineering prototype boards with built-in LPC1768 and LPC11U24 MCUs, which has shipped over 15,000 units; and the NGX Xplorer evaluation/development boards with built-in LPC1800/LPC4300 MCUs. In addition, other evaluation/development boards include those developed by Embedded Artists, IAR, Keil/ARM, Code Red, Hitex, Embest, and NGX.Regarding a free software library; NXP provides open source, nxpUSBlib library for USB control, Free Lightweight IP (LWIP) library for Ethernet network control, and emWin graphics library for GUI interface. Regarding real time operating systems (RTOS); μC/OSII or μC/OSIII developed by FreeRTOS and Micrium or μCLinux developed by EmCraft are free and downloadable online.Finally, regarding technical support; NXP has established the LPCware.com website to provide education and training, software and driver download, engineering schematics, development tool download, FAQ, and design technique discussion and information. Educational training video clips are also available at the lpczone channel on YouTube. Finally, NXP LPC microprocessor discussion information can also be found in social networking sites such as Yahoo, Twitter, YouTube, and Facebook as well as exclusive community websites such as LPCware, LPCXPRESSO, and mbed.Jeff Liu, technical marketing manager of NXP Semiconductors (NXP) in Taiwan

Phoenix SecureCore Technology (Phoenix SCT) 3.0, the latest UEFI BIOS firmware from Phoenix Technologies, uses a graphical user interface to simplify once obscure BIOS settings. It uses an integrated development environment to accelerate firmware development, debugging, and customization in order to enhance boot performance while providing peripheral and system security support. Phoenix SCT 3.0 is playing a significant pioneering and innovative role in the next generation of BIOS. It is the first firmware in the industry to provide native EDK II support, backward compatibility support for EDK 1117, and cross-border applications for tablet PCs, ultrabooks, embedded systems, and servers.Phoenix SCT 3.0 - Pioneering and innovativeIn the past, BIOS used a text mode interface, with computer engineers having the knowledge to understand an item's meaning. The old model of control interface no longer meets the needs of today's prevailing touch control mobile devices. Terry Chen, VP Development Engineering at Phoenix, said during the recent DTF 2013 Embedded Technology Forum that Phoenix is committed to providing a simpler and more intuitive BIOS interface for end-users. Phoenix SCT 3.0, launched at the end of 2012, is equipped with a brand new graphical user interface BIOS setup.Chen said that Phoenix SCT 3.0 is based on the latest UEFI specifications and the next generation UEFI BIOS EDK II core build environment. It provides backward compatibility to the previous generation's EDK 1117 specifications, and its unique universal framework system can provide cross-platform support for x86 and ARM architectures, simultaneously supporting different operating systems such as Windows and Linux, and can meet the needs of multi-platform generation system development with a single BIOS core.Smooth migration to EDK IIChen said that the packages, building tools, library objects, and configuration settings of EDK II are vastly different than those of EDK 1117. Intel is only scheduled to migrate to the EDK II firmware codes no later than 2015; therefore, a smooth transfer to EDK II is critical. Currently, the existing EDK program codes/library resources have not been fully migrated. If both the EDK 1117 and EDK II systems were used simultaneously to write firmware code, it would cause resource investment duplication and management problems.Phoenix Technologies has proposed a universal build system that can simultaneously support EDK 1117 and EDK II program codes and drivers. The system's program code foundation is comparable to distinct IHV principles, and remains compatible with the older SCT .def usage, as well as the new EDK II PCD macro language definitions to assist customers with a smooth migration to EDK II.Support and enhancements for Windows 8Chen stated that Phoenix SCT 3.0 has added numerous new functions to the Windows 8 platform. For example, Fast POST can decide whether to initialize USB devices to save boot time. Microsoft uses the S4 sleep mode for fast boot-up and may not be able to detect newly installed hardware, but Phoenix SCT 3.0 can fix this situation.Many automated software tests used on production lines will not work if the Secure Boot option in BIOS is activated. The Auto Signature Enroll Utility designed by Phoenix can configure the BIOS to activate Secure Boot during the last shutdown after all the products have been detected. In addition, Phoenix SCT 3.0 also supports the random number generator (RNG) agreement provided by EFI firmware or hardware during Windows boot-up, as required by Microsoft.When a tablet PC activates the BitLocker hard disk encoding mechanism, the touch IC driver is integrated into the protective TPM encoding block and cannot be initialized during the boot process. This prohibits the tablet PC's virtual keyboard from being activated during the boot stage and being used to enter passwords. However, Phoenix SCT 3.0 can pre-initialize the touch control mechanism during the boot stage and allow users to perform BitLocker unlock using a virtual keyboard. In addition, for tablet PCs requiring external USB LAN Dongle (USB to LAN adapter) connections, Phoenix SCT 3.0 can support the LanBoot PXE with USB to LAN adapters and provide USB device boot support for Windows To Go (WTG).Chen indicated that Microsoft has proposed allowing BIOS, TPM, IC readers, and even LAN network firmware to be downloaded and updated automatically through the Windows EFI Firmware Update (WUFU). Phoenix SCT 3.0 already provides full support for the NIST SP 800-147 (Secure BIOS and Secure Flash) security specifications, the Non-volatile Capsule Update mechanism, and reserves future support for WUFU. Phoenix SCT 3.0 also supports S0ix required by Connected Standby and PUIS (Power Up In Standby) modes as defined by Microsoft.Modern screen settings and excellent user experiencesChen emphasized that Phoenix SCT 3.0 can hide some sensitive/critical setting options required by the customers which can be displayed through special hotkeys. In some cases, File Explorer can also be embedded in the BIOS setup screen to provide functions that are similar to Windows Explorer. This allows users to organize files and directories, download files online, or delete files for drivers on the hard disk prior to reaching the OS stage.Phoenix SCT 3.0 can directly initialize and provide support for touch ICs during the boot stage and provide BIOS touch hot-zones. Even without a keyboard, users can trigger various functions by touching the various parts of a touchscreen. For example, users can enter BIOS setup by touching the upper-right corner of the screen, or enter the Boot Menu by touching the lower-right corner of the screen, or even activate the Windows Key by touching the lower-left corner of the screen. Chen also mentioned that since the default text size is 19 points for the Intel UEFI firmware codes, text is hard to see on a 7.5 inch tablet PC and cannot be accurately controlled by the touchscreen. To solve this problem, Phoenix SCT 3.0 provides an adjustable font size browsing mode.The biggest change for Phoenix SCT 3.0 is the latest Windows 8 style GUI BIOS Setup that utilizes finger touch control through a floating keyboard. Even gesture control is planned in the future.OEM/ODM system developers can use the Phoenix Desktop Manager (PDM) customizable graphical user interface core engine to easily design exclusive graphical interfaces with WYSIWYG real-time text/color adjustment control methods that are similar to Windows.Using BIOS applications to create added-value for embedded systemsAnother feature of the PDM is that before an OEM device is registered by Windows during boot, it can pre-load the extension platforms that run the UEFI app programs, creating critical vendor differentiation in the embedded systems market. For example, the calculator, or QR Code programs can be directly executed during the BIOS stage without having to wait until Windows is booted.In the past, BIOS firmware usually had to be fully rebuilt because some preloaded EFI drivers had to be removed in order to accommodate production line automated testing. Through the universal customized system (UCS) under the Phoenix SCT 3.0 development environment, several drivers and functional combinations can be selected and written into the BIOS firmware, and be defined by the runtime feature control jumper bits. When the system boots, the BIOS firmware enables Phoenix SCT 3.0 to perform the corresponding driver initiation/function combinations based on the jumper settings on the motherboard. This prevents production lines from having to wait for BIOS engineers to modify firmware before tests can be performed.Improve system integrity and securityPhoenix SCT 3.0 provides additional system integrity improvements: (1) Sure Boot provides BIOS Auto Fail-Over that enables the system to select the most conservative factory-default settings during boot; (2) Safe Recover BIOS2 provides dual firmware backup/repair mechanisms to reduce the probability of RMA repairs due to BIOS damage; (3) Debug support capabilities that record the error register and flag states, memory addresses, and possible debugging information into the non-volatile memory via UEFI BIOS Capsule Update when the blue screen of death appears under the Windows 8 environment; and (4) a Non-Volatile Capsule that directly records the parameter setting values into the protected GPT Partition and reboot to replace the sleep wakeup boot mode.Regarding security enhancements similar to the Secure Boot stage defined by Tiano (UEFI), Phoenix SCT 3.0 ensures that only reliable software and firmware can be executed and adds BIOS system parameter write protection as well as UEFI RAID OPROM password support.Chen indicated that as a solution for the embedded market, Phoenix SCT 3.0 can help embedded system developers to smoothly migrate from existing Legacy/EDK 1117 firmware to EDK II to create a universal system platform and provide synchronized support for Windows 8 Embedded. Phoenix SCT 3.0 can provide a scalable text setting screen as well as touch and graphical configuration interfaces that can apply to embedded mobile devices and tablet PCs, and provide BIOS damage auto-repair mechanisms and proposed WUFU support to enhance system reliability that meets the present and future security needs of Windows 8.Developed under the EDK II architecture, Phoenix SCT 3.0 UEFI BIOS can smoothly migrate from the software code resources of EDK 1117, taking into account future cross-platform portability of the ARM architecture while providing a better user experience and connectivity, support for embedded servers and embedded applications, and create differentiated product value for customers.Terry Chen, VP Development Engineering at Phoenix

The defense, aerospace, transportation, outdoor, mining development, high temperature, and chemical industry fields often encounter extreme or corrosive chemical environments. Advantech, which provides services for long-term management of embedded applications, has proposed embedded application solutions for these types of extreme environments.Extreme environments bring new challenges and opportunities for embedded applicationsAaron Su, Embedded Core Group/COM Product Manager for Advantech, indicated that industrial automation as well as cloud and smart computing are the two major trends that will spur a new wave of market opportunities for embedded applications. Extreme temperature changes provide a great challenge for the temperature tolerance of embedded devices. Extreme climates caused by greenhouse effects as well as resource depletion challenges are similar to challenges faced by a coal mine digging machine after it has dug the surface and is moving underground, which has to overcome different geothermal and environmental pressures.The key design features of extreme environment industrial control products are: higher product stability is required to reduce future maintenance costs; wide-range temperature embedded devices for single-task RTOS that do not require high computing capabilities; and longer warranty and supply periods. Risky industrial control applications for the military, aerospace, transportation, outdoor, mineral resources development, high-temperature, or chemical fields are all within the scope of extreme environment applications. To overcome extreme environments, embedded systems must be heat resistant as well as provide compression and seismic reliability, stability, waterproofing, and anti-corrosion features. These requirements can be overcome through designs, materials, and stringent verification.Embedded solutions for wide-range temperature fluctuationsSu indicated that from the initial design stage, materials and parts that do not meet the working temperature requirements must first be identified to save time and subsequent development. Product design must go through functional design testing as well as heat source simulations and analysis. In particular, to ensure stable operation in a wide-range temperature environment when some materials and parts in the wide-range temperature product are still under normal temperature specifications, Advantech has designed onboard overheat protection mechanisms to prevent materials and parts from overheating and crashing, as well as low temperature activation to enable materials and parts to reach working temperatures rapidly and maintain normal operation. In addition, power efficiency must be considered to enable devices to operate longer in areas that lack electric sockets.Wide-range temperature product verification is divided into developmental verification and shipping verification stages. During the developmental stage, engineering samples/systems are fed into a chamber and then activated to perform full-load operations; thermal shock tests are then performed by rapidly and repeatedly moving the test products between high and low temperature environments; and finally, over 50 hours of full-load burn-in and power outage/restart power cycling tests are also performed. 100% of the products must also be tested during mass production where each systems must be burnt-in to confirm normal operations before shipping to the customers. In addition to burnt-in tests, reliability tests such as Highly Accelerated Life Testing (HALT) can also be performed to detect product weaknesses and select appropriate improvement or reinforcement measures to improve the tolerability of products.Waterproof/corrosion resistance/seismic solutions for embedded products and peripheralsSulfide particles in the air around ships, chemical plants, outdoor mass transportation (such as trains), and industrialized countries with severe air pollution problems often cause corrosion and damage to embedded motherboards. Su further introduced waterproofing and anti-corrosion applications and indicated that moisture-proof, dust-proof, anti-corrosion, and anti-friction effects can be achieved by performing Conformal Coating Services on the PCB surfaces of motherboards. Materials used include acrylic (AR), urethane (UR), silicone, and epoxy (ER). Each of these materials has unique repair, moisture resistance, abrasion resistance, solvent resistance, mechanical tension, and elasticity characteristics that are suitable for certain objectives.Protective coatings can be applied manually or mechanically. Manual coating is used during small test production, and the drawback is that it is unable to achieve a uniform coating. Advantech provides mechanical automation coating services using acrylic resin or organic silicon as the coating materials. Under IPC-610D specifications, the maximum coating surface is 450mm by 450mm with thickness ranging from 0.5mm to 5mm. On average, coating for one motherboard can be completed in three minutes. The coating can enhance the waterproof, moisture-proof, anti-salt atmosphere, anti-friction, anti-metal particle, and anti-bacterial capabilities of boards.There are currently four solutions that can improve the shockproof and warpage-resistant capabilities of a system: solder chips such as CPU and memory onto the motherboard as much as possible; apply glue on both sides of memory modules to avoid shaking and shedding; use locked connectors with retaining clips for connectors/slots; and use lockable flash storage modules.The IEC60068-2-64 specification is compiled for anti-vibration tests where the maximum vibration acceleration force and frequency can reach 5G and 5Hz to 500Hz. The IEC60068-2-29 specification is compiled for impact tests (with the maximum impact force set at 15G). In addition, Corner Bonding can be performed on chips to increase the PCB thickness as a solution to prevent PCB board warpage from causing BGA chips to crack.Su pointed out that Advantech also provides a full series of industrial wide-range temperature peripheral devices. These devices include the SQFlash storage module series (with PATA/SATA/USB interfaces and a three-year warranty) and the SQRAM memory module series (wide-range temperature, Goldfinger 30nm plating processing, Fix Die chip bonding, and thermal sensor designs). The wireless transmission module provides wide-range temperature and seven-year warranty as well as wide-range temperature and high illumination touch control display equipment. Advantech's Rugged Industrial Display Solution enables normal operation between minus 20 to 60 degrees C and provides readability of 1,200nits under normal sunlight. The solutions include rugged, stand-alone monitors with IP54 front panel protection and tempered glass. The life span of the backlight reaches 50,000 hours.ARM's opportunity in low-end embedded devices and intelligent nodesAt present, hardware developers such as AMD, Freescale, TI, and Nvidia have adopted industry specifications such as PCI Express, USB, and SATA. Microsoft and Google have launched the Windows RT and Android operating systems, respectively. Industrial control field players such as Kontron, Congatec, and MSC are promoting Q7 and ULP form factors. According to ARM's market data, in 2011, ARM's mobile device market saw a 15% gain and reached US$4.5 billion, the embedded device market division saw a 70% gain and reached US$7 billion, enterprise applications had a 30% gain and reached US$1.3 billion, and household devices had a 10% gain and reached US$300 million.Su said he believes that the ARM RISC architecture with low power consumption (<3W), wide-range temperature (minus 40- to 105-degrees C), SoC design, and rapid boot features should be preferred by customers. At present, ARM's products are low priced. However, overall development costs are higher than for x86, and information acquisition costs are not as diverse. Because ARM's level of standardization is not high and its cases are mostly project design in nature, there is a higher moral risk for customers and specific hold up costs. This restricts ARM's penetration in the low-end embedded application market.To integrate industrial control applications into cloud computing architectures under the intelligent earth concept, sensors provide downstream transmit data using wireless or wired methods to intelligent nodes with ARM cores. Data are then connected to a computing core (x86-based) at the next higher level and then are eventually uploaded to the cloud server. The functions of the intelligent nodes are to connect the sensors and the cloud as well as provide the underlying intelligent computing capacity for the cloud to disperse load and make the system more efficient.Strengthening ARM through early designs and integrated supportBased on Su's analyses, RISC clients are categorized as in-house, outsourcing, early-comers (pragmatists), late-comers (followers), and laggards. The first two categories focus on product price/overall development costs. The early-comers (pragmatists) appear in the design standard stage and are restricted by company size and development capabilities; therefore, they cannot independently develop ARM core applications and need to switch to x86 solutions. This category of clients focuses mostly on the first four costs mentioned above. Late-comers (followers) select ARM solutions due to market trends, low RISC price factors, and customer demand; and mostly focus on price/overall development costs and specific hold up costs. The characteristics of laggards are that they refuse to integrate ARM solutions due to non-technical or non-market driven reasons, such as being Intel partners.Promoting ARM standardization can resolve the moral risk costs and specific hold up costs; closely connect the upstream and downstream to resolve information acquisition costs; and resolve these costs by replacing trade with a collaborative design methodology.Regarding form factor standardization; Congatec launched the Qseven(Q7) in 2008 and Advantech launched its RTX 1.0 in 2008, Kontron during late 2012, and RTX 2.0 for rugged applications in 2013. RTX 2.0's shockproof design and 2mm PCB thickness can prevent board warping and cracking. RTX 2.0 adopts the B2B connector which is similar to that of ETX specifications, has a multi-function heat-sink design, and is more suitable for rugged industrial control applications than Q7 and ULP. Finally, Su mentioned that the ARM RISC architecture's collaborative design methodology can replace the traditional trade model. For example, Advantech provided R&D manpower and design support from the early developmental stages of U-Boot and BSP/Driver. After the products began selling to the client-side, Advantech continued to provide design-in services to assist clients in completing their projects, which in turn reduced the clients' difficulty in adopting the ARM-core products.Aaron Su, Embedded Core Group/COM Product Manager for Advantech

The quality and durability of successive generations of flash memories have tended to drop. Industrial customers are often only willing to use costly SLC memory, which limits SSD capacities for industrial control applications. The flash SSD/DOM industry has incorporated iSLC memory technology which is 10 times more durable than MLC, as well as key technologies that can maintain and monitor program/erase (P/E) wear leveling. This allows MLC to be integrated into lightweight industrial control applications, while iSLC memory will become the new darling of industrial control applications.The challenges of MLC in embedded industrial applicationsAs production processes have advanced, the line width and spacing of NAND flash have become increasingly smaller, which has reduced the number of P/E cycles. Taking SLC memory as an example: the 100,000 P/E cycles of 3xnm process era chips required only four ECC (error correction code) bits; while the P/E cycles for SLC in the 2xnm process era have reduced to 60,000 and 24 ECC bits are required.The early 5xnm production process MLC flash required eight ECC bits with 10,000 P/E cycles, and during the 3xnm MLC era, P/E cycles were reduced to 5,000 while ECC significantly increased to 15 bits. During the 2xnm MLC era, P/E cycle have fallen to 3,000 and ECC expanded to 24 bits, and 2ynm node MLC requires 40 ECC bits.Transmission rates of peripheral storage devices have also continuously improved. In 2010, ONFI 2.0 was advanced to 133MB/s and transmission rates of eMMC v4.41 were 104MB/s. In 2011, the ONFI v2.2/Toggle 1.0 specification increased flash transfer rates up to 200MB/s, the eMMC v4.5 was raised up to 200MB/s, while the transfer rate of UFS 1.0 was 2.9Gbps, and the SATAII specification was 3Gbps (300MB/s). In 2012, the ONFI v3.0/Toggle v1.5 specification raised flash transfer rates up to 400MB/s, UFS v2.0 transfer rates doubled to 5.8Gbps, and the SATAIII specification jumped to 6Gbps (600MB/s). By 2015, the transmission rate of the ONFI v4.x/Toggle v2.xx specification is expected to increase to 800MB/s and 1.6GB/s.Facing the various challenges from the declining durability/quality of flashCC Wu, Director of Embedded Flash Business Division at InnoDisk, listed the challenges of the MLC memory as follows: The number of error bits continues to increase; 40 ECC bits are needed at the 2ynm node and the number will continue to increase at temperatures around the negative 40 to 85 degree C range. Meanwhile, sudden power interruptions during power cycling often cause data to become lost, the lifespan of data decreases as P/E cycles increase, and the 16K paging design of MLC takes a significant amount of processing time for garbage collection.If customers want to integrate MLC into lightweight industrial control applications, good P/E wear leveling and internal monitoring tools are required, in addition to other complementary technologies.As the number of P/E cycles increases, error units also increase. Taking 3xnm MLC as an example: according to internal long-term test results performed by InnoDisk, an average of one error will occur within 1,000 P/E cycles. Beyond 20,000 P/E cycles, the number of errors increases five-fold. For 2xnm MLC, the average number of errors for less than 1,000 P/E cycles is already five, and the errors increase to 25 for 8,000 P/E cycles. For 2ynm process MLC, the number of errors is three for 1,000 P/E cycles, 34 for 8,000 P/E cycles, and 41 for 10,000 P/E cycles.InnoDisk indicated that flash Correct-and-Refresh (FCR) technology can read and monitor MLC blocks where the occurrence rate of errors has increased, fix the error bits, and store them in better conditioned blocks, and then restart the P/E cycle to improve the service life of the flash. InnoDisk has also developed smarter garbage collection algorithms for 16KB paging MLC flash to reduce the SSD data maintenance delay phenomena.Wu believes that during access to MLC memory, dynamic wear-leveling technology can be used in combination with static wear-leveling technology which is especially critical for MLC with just 3,000 P/E cycles. InnoDisk has provided an iSMART utility program that can illustrate the number of times an SSD block has been written to, and illustrate the overall wear-leveling effects. It can also monitor temperatures, estimate service life, and provide performance monitoring and pre-warning functions.If a sudden power outage occurs when MLC is writing data and the firmware is performing data writing or garbage collection, it is likely to cause damage to the memory page where the data is being written, and the adjacent memory pages, and may even cause the entire SSD's data to become lost. Therefore, a good SSD controller must have failure/low-voltage detection circuits that can quickly finish writing data to memory pages and save any necessary system-state data for restoration, in order to enable a reboot when a drop in input current voltage is detected.Using iSLC to provide low-cost and high-quality industrial control applicationsIndustrial control applications under general commercial temperatures (0 to 70 degrees C) require constant read/write capabilities and a five-year quality guarantee. Customers mostly choose SLC for heavyweight intensive read/write applications. However, SLC costs almost five times more than MLC. Therefore, InnoDisk has proposed the iSLC memory solution.iSLC has the advantages of both SLC and MLC. It is produced using existing low cost MLC memory process technology, and has SLC-like read/write capabilities (each charge stores only 1-bit). Therefore, endurance is improved to 30,000 P/E cycles, falling between the 60,000 P/E cycles for SLC and 3,000 P/E cycles for MLC. Although iSLC involves higher costs than MLC, it is half the cost of SLC and can be applied to IPC/kiosk/POS systems, embedded systems, server boards, thin terminals, etc.Wu illustrated a long-term durability test chart for MLC and iSLC produced under the same 2xnm process. The results showed that after 20,000 continuous data writes, MLC generated over 30 errors while iSLC generated only six. Even after 100,000 continuous P/E cycles, iSLC generated less than 10 errors and its durability and quality are comparable to those of the SLC memory created under standard SLC processes. The results for 32GB SSD tests showed that when 32GB of data is written 10 times each day, MLC can only be maintained for 0.8 years, 3xnm SLC can reach 27.4 years, 2xnm SLC can reach 16.4 years, and 2xnm iSLC can reach 7.6 years.InnoDisk has designed a series of products using iSLC flash memory technology for the SATAII interface. Its 2.5-inch SSD 2IE model adopts an 8-channel design, offers between 32GB and 256GB capacities, and has a sustained write speed of between 200MB/s to 230MB/s; the SATADOM-QVL 2IE and SATADOM-QV 2IE models adopt 4-channel designs, come in 8GB to 64GB capacities, and have sustained write speeds of between 120MB/s to 130MB/s; and the CFAST 2IE adopts a 4-channel design, capacities between 8GB and 64GB, and has a sustained write speed of between 120MB/s to 130MB/s. In addition, the company offers 2IE mSATA, Slim 2IE, and SATADOM QH 2IE modules that adopt a 4-channel SATAII design, come in 8GB to 64GB capacities, and offer sustained write speeds of between 120MB/s and 130MB/s.SATAIII solutions for embedded applicationsWu then introduced SATAIII product solutions for embedded industrial control applications. The InnoDisk ID167 control chip developed by InnoDisk adopts a 4-channel 8CE design, and has an ECC data correction capability of 40bit/1KB. It uses a 64MB 16-bit DDR III memory read/write buffer and consumes between 5mW and 33mW of power under SATAIII slumber and DEVSEL modes. SSD and mSATA modules designed with the ID167 will begin sampling during the first quarter of 2013.InnoDisk's ID167 adopts 24/25nm process Sync MLC flash memory chips. Under IO Meter performance test, the 64GB (4CH) version delivers sequential read/write performance of between 270MB/s and 480MB/s and sustained read/write IOPS are 1K and 80K. The 128GB (4CH) version, offers sequential read/write performance between 350MB/s and 520MB/s and sustained read/write IOPS are 2K and 80K. For the 256GB (4CH) version, sequential read/write performance can reach between 400MB/s and 550MB/s and sustained read/write IOPS are 3K and 80K.Compared to 128GB SLC SSDs used in mainstream industrial control applications, CystalDiskMark v3.0 test results indicate that the sequential read/write speeds of the 256GB MLC SATAIII SSD are 519MB/s and 344MB/s, respectively; and the sequential read/write speeds for the Pure SATAII 128GB SLC SSD are 253MB/s and 190MB/s, respectively. At similar costs, the 256GB MLC SATAIII SSD has twice the capacity and faster performance compared to those of the 128GB SLC SATAII SSD.InnoDisk also provides single-chip modules. The 32GB (4CHx1CE) comprises the InnoDisk ID167 controller chip with a flash silicon wafer chip on board (COB) package. The device has sequential read/write speeds of 480MB/s and 140MB/s, respectively. When CystalDiskMark v3.0 performance tests are conducted to compare performance against the 32GB SATADOM SATAII SLC, the sequential read/write speeds of the SATAIII device are 482MB/s and 271MB/s, respectively; and the SATAII sequential read/write speeds are 252MB/s and 235MB/s, respectively.CC Wu, director of embedded flash business division at InnoDisk

Today, the importance of hardware virtualization has continued to increase from home entertainment to the mobile market. A higher level of security and content protection can be achieved through hardware virtualization. An increasing number of consumers have used such hardware virtualization to perform mobile payments, HD media streaming, Cloud storage, or even secure ID protections where highly secured applications are required.Imagination Technologies has released MIPS Release 5 (R5), which is an important new version for the MIPS architecture. The new architectural enhancements that underwent more than two years in development process include critical functions such as Virtualization and Single Instruction Multiple Data (SIMD) modules. The MIPS virtualization modules have highly scalable options with multiple functions, including enhanced security features and support for multiple operating systems.Rao Gattupalli, Director of Segment Marketing at Imagination indicated that, "Virtualization is an essential key to the future development of embedded systems." Regarding the development of the embedded systems security architecture, Gattupalli stated, "We must first define what we mean by a security system. The most precise definition is that if a system can ensure smooth operation without unintended data leakage/loss, it can be regarded as a safe and reliable system."Isolation: The key to system securityThe urgent security needs of the embedded system cover a wide dimension ranging from consumers to enterprises. From the consumer perspective, Gattupalli pointed out that smart phones and tablet PCs have become targets for hackers. Furthermore, rapid software development and increased software complexity have prevented full software integrity verifications, thus causing the error/hacker attack problems to become increasingly serious.In the corporate field, bring your own device (BYOD) has become one of the biggest security challenges. In addition, awareness for content protection and media streaming security as well as the needs for secure payment transaction spurred by mobile payment, secure Cloud storage, and secure ID protection are on the rise. The new generation of embedded devices require solutions that provide more security while taking into account the SoC area and cost benefits. Gattupalli indicated that one of the key objectives to SoC design in response to the demands for modern embedded security is to isolate secure applications from non-secure applications in order to ensure that data transmitted during secure applications are not stolen or leaked.An embedded application specific secure SoC must be able to isolate secure data from non-secure applications. Currently, this isolation mechanism is required from smart phones to set top boxes (STB) because increasingly more applications require complex terminal equipment to process high security content such as encryption keys, payment systems, and HD video streaming. Gattupalli indicated that, "Within one system, protection is required from one application to another and from one data type to another." Meanwhile, these applications must operate smoothly without interruption. That is, when operating system error occurs in another area, the application must be able to continue to run or exit intact.In general, the secure partition construction method includes using another core or using the virtualization technology to create multiple secure and non-secure partitions within a single core. Virtualization can be accomplished through para-virtualization or hardware-assisted virtualization. MIPS can enable a solution that can support both para-virtualization and hardware assisted virtualization simultaneously. At present, the market already has a para-virtualization solution that can be implemented on MIPS-based cores. Furthermore, the MIPS architecture also provides the hardware-assisted virtualization technology.Gattupalli indicated that numerous SoCs currently adopt the dual-core processor configurations where one processor is responsible for the non-secure area and the other is used for the secure area. Today's security configurations are universal and can provide a high level of security. However, greater scalability and cost-effectiveness methods are still needed in practical applications to satisfy the needs of the new generation devices to simultaneously perform a variety of applications within the security area.Use secure SoC as the core for embedded systemsGattupalli first specified the six key elements that constitute a secure SoC as follows: secure boot, secure key storage, trusted execution environment (TEE), secure data path, secure update, and secure debug.Secure boot is referred to as the root of trust that is primarily used to prevent tampering. It is usually the read-only memory used to store the initial start-up code required for device reset. Secure key storage generally means the OTP OPT area used to store secure assets such as public keys and other DRM encryption keys. For example, the Netflex video on demand application stores the public key in the OTP OPT in order to decode the contents. Safe boot and secure key storage is the primary objective of constructing a secure SoC.The TEE software layer is loaded after the successful load and certified initialization of the program. The TEE is the secure environment used to manage and control access to a set of low-level software modules. These sub-modules include security keys, secure data paths, secure updates, and secure debugging. The TEE is used for the allocation of resources and prevents non-secure applications from accessing the secure block. Basically TEE can be regarded as the gatekeeper of the bottom-level hardware resources. For example, during STB applications, the TEE can ensure that unauthorized applications cannot access critical assets such as the unencrypted address of the secure data that may exist in the video codec or the memory.Secure data paths can ensure that high-value assets such as codecs can only be accessed by authorized entities. Secure update is to provide validation and management to ensure safe upper level system software updates. Gattupalli indicated that because operating systems, and various peripherals such as USBs all require updates; therefore, customers will need the security safeguards during the updating process. In addition, debugging also has security needs. The secure debug module for the SoC can enable the JTAG port to prevent unauthorized access.Gattupalli further indicated that, "The biggest challenge for the SoC secure embedded application comes from power and size as well as the reusable resources for secure and non-secure applications." He specifically emphasized the importance of reusable resources. As terminal devices become more complex with the development trending towards multi-core processors, the lack of reusable resources for secure and non-secure applications is bound to create numerous design drawbacks.The other major challenge comes from the multiple secure zones. Gattupalli indicated that general single- or multi-user data access, enterprise-level data access, and financial or personal data access operations are all major challenges for the secure SoC. Meanwhile, before these needs are fully satisfied, designers would also hope to optimize the SoC size and costs. The virtualization technology is the best solution for this situation.As the virtualization technology can enable parallel processing of multiple operating systems and applications while consolidating workloads, it can be used as the key technology to develop the next generation security-critical embedded devices. The MIPS virtualization module is a simple and flexible hardware solution that can satisfy these different needs under the limited or unaffected performance setback conditions.Virtualization brings greater benefits to the embedded systemVirtualization provides a scalable and TEE for the secure embedded system to connect to a variety of applications. It can secure isolation for each individual environment and manage privileged resources through access policies defined by each virtual machine. Meanwhile, only the trusted execution environments can communicate with the virtual machine. These features not only strengthen the reliability of the system, they can also accelerate the speed developments in the future.Virtualization allows multiple independent operating systems on a single processor to become completely isolated, such as running Linux and RTOS simultaneously, while strengthening system reliability. That is, a session malfunction would not cause the entire system to fail. In addition, virtualization can also help to implement QoS, contribute to the migration from heterogeneous to homogeneous multi-core, and protect the customers' investments in operating systems and real-time operating systems.In fact, Gattupalli indicated that the core element of virtualization is hypervisor, a small code constructed on the hardware to provide a reliable execution environment. Hypervisor can manage resource priority by defining the access strategy of each execution environment or "object." The objects will be isolated from each other, but can communicate to each other through a secure API and hypervisor. System reliability can be achieved through secure operation from other entities beyond the guests, and the system would be unaffected even when one guest is damaged. Hypervisor can manage all of the I/O priorities for the memories of the subsystem.Gattupalli indicated that secure hypervisor can serve as the foundation for embedded systems that emphasized on security and reliability, virtual environments can provide flexible software management, and the software and hardware security virtualization solutions for MIPS would become the key to enable the embedded system design to reach its goal quickly and successfully.Rao Gattupalli, Director of Segment Marketing at Imagination