As the AI computing race accelerates and semiconductor manufacturing capacity is increasingly redirected toward advanced memory, the memory industry is shifting from price-driven competition to a battle over resource allocation and supply security. The rapid expansion of high-bandwidth memory (HBM) production continues to consume advanced fabrication capacity, constraining the supply of conventional memory products and creating persistent shortages across the market. This concentration of high-end production has widened the supply-demand gap, driving the average selling prices of certain premium memory products to levels eight to ten times higher than previous norms

Rugged edge computing brand – Cincoze will showcase its latest embedded computing solutions at COMPUTEX Taipei 2026, from June 2–5 (Hall 2, Booth Q0401a). Cincoze will display its full range of edge computing solutions around the theme of "Smarter, Faster, More Reliable - Powered by Edge AI" encompassing the full spectrum of edge application environments in four dedicated zones, including DIN-Rail computers, industrial panel PCs and monitors, rugged embedded computers, and GPU embedded computers

Technology news, product launches and show highlights from the event attendees available for download (PDF).

Rapid evolution of High-Performance Computing (HPC) and artificial intelligence chips for Hyperscalers and tech giants continue pushing large sized silicon demands. As a core element of semiconductor value creation, advanced packaging technology is scaling the stacking of more computing cores, more high-bandwidth memory, as well as the adoption of modular chiplet integration to overcome physical boundaries. Leading semiconductor manufacturers are expanding package dimensions to unprecedented footprints, currently reaching sizes of 100, 120, with projections moving beyond 180 mm to support large-format AI-driven advanced packages.The semiconductor industry is responding and shifting toward solutions that combine large-scale mass production with large-format packaging capabilities. Square sized substrates offer a distinct area utilization advantage to accommodate more large-form-factor chips simultaneously by moving away from round wafers to large rectangular panels. This is improving cost efficiency and addressing the challenges of thermal warpage and high-density interconnects associated with massive AI packages.Glass substrates are emerging as a key technology for advancing panel-level packaging from pilot experiments to active equipment qualification and commercialization verification. Consequently, Redistribution Layer (RDL) wet process and ECD equipment has become a critical driver of this transition and a key step in glass substrate manu-facturing. Key production tools including Electrochemical Deposition (ECD), cleaning, developing, etching, and stripping are not only vital to glass core substrate manufacturing, but also central to achieving high yields and mass production capabilities in advanced packaging technologies such as fan-out panel-level packaging (FOPLP) and Chip-on-Panel-on-Substrate (CoPoS). The wet processing equipment has garnered significant market attention.Omni production platform supports cross-sized substrates in 310, 510 and 700mm panelManz Asia, has successfully delivered Omni 310 system, which is the world’s first $310\text{mm} \times 310\text{mm}$ ECD wet chemistry system in early 2026. The system uses an electrochemical deposition module as its core, combining wet processing tools including cleaning, developing, plating, etching, stripping, and dual mechanisms support for both spin and spray operation. This new platform addresses the adaption to varying rectangular substrates.At SEMICON Taiwan 2026, Manz Asia expanded its portfolio with the launch of the cross-sized Omni series production systems. Engineered for varying panel dimensions, packaging architectures, and strict process requirements, this series feature the Omni 310, Omni 510, and Omni 700 to deliver optimized panel-level packaging (PLP) solutions across 310mm, 510mm, and 700mm panel sizes to meet the requirements of advanced PLP technology roadmaps including FOPLP, CoPoS, and Glass core TGV manufacturing.Take early-move positioning for Glass Core substrate aiming to tackle Through-Glass Via challengesRapid advancements in CoPoS are driving the shift from organic substrates to Glass Core, with TGV metallization, seed-layer formation, and copper via filling emerging as key process challenges. The Omni Series RDL platform integrates glass surface modification, cleaning, electroless copper plating, and electroplating to enhance copper adhesion and enable reliable TGV metallization and filling. Major Benefits of Omni series include.High performance ECD technology: The system offers excellent capabilities for filling high-aspect-ratio through-vias. When combined with an optimized seed layer and specialized plating chemistry, this process enables void-free via filling, delivering a highly stable and critical solution for electroplating on glass carrier substrates.High-precision glass etching technology: Featuring robust glass micro-machining capabilities, this technology supports the processing of 0.4 mm glass substrates and the creation of $20\ \mu\text{m}$ micro-vias. It offers TGV process capabilities with aspect ratios of up to 1:20, providing a critical advantage for achieving deep, fine-featured vias. Therefore, the system addresses the challenges of high-density TGV designs and marks a milestone in establishing a mass-production platform for next-generation packaging architectures.Empowering Heterogeneous Integration with advanced RDL for High-Precision Multi-Layer InterconnectionWith 40 years of in-house R&D expertise in RDL processing, Manz Asia has developed extensive expertise across PCB, IC substrate, display panel, and semiconductor packaging applications, and is now building strong collaborations with global IDM and OSAT clients. By helping customers accelerate key process iterations and transition smoothly to mass production, Manz Asia plays an active role in the global RDL processing and panel-level packaging supply chain.Designed for next-generation advanced packaging technologies like CoPoS, FOPLP, and Glass Core TGV, the debut of the Omni series production systems helps customers accelerate their transition from R&D validation to mass production. To learn more about Manz Asia production systems and product offerings, please visit the booth M1248, 4th Floor, Hall 1, Nangang Exhibition Center at SEMICON Taiwan 2026. You can also view detail product information on the official website.

At SEMICON Taiwan 2026 Booth T9116, SiliconAuto will showcase automotive-grade silicon solutions for Physical AI, developed through collaboration across Taiwan's world-leading semiconductor ecosystem. Visitors can experience live demonstrations of technologies designed to power future robotics and autonomous driving applications. The solutions are built on the XMotiv M3 microcontroller and high-performance computing (HPC) platforms used in intelligent vehicles and robots.Throughout the exhibition, the SiliconAuto team will be on hand to discuss practical approaches to Physical AI development. Topics range from semiconductor architecture and system design to multi-die integration and packaging. Visitors can also get hands-on with XMotiv M3 developer kits for robotic motion control, automotive body control, and safety orchestration.Automotive-Grade Silicon, Purpose-Built for Safe and Secure Physical AIExperience SiliconAuto technologies in action through three demonstrations, spanning robotics, autonomous driving, and high-performance computing. First of all, the XMotiv M3 as an ASIL-B Robotics Controller. In collaboration with Nexuni, a Taiwanese robotics developer focused on bringing AI-powered robots into practical, everyday applications, SiliconAuto is debuting a robotic motion control developer kit. XMotiv M3 controls dynamic stabilization through joint actuators. The demonstration highlights XMotiv M3's high-speed interface capabilities. These capabilities enable real-time control. ASIL-B compliance lays the safety and security foundation.Secondly, XMotiv M3 for Autonomous Driving. See how MCU XMotiv M3 works alongside ZF's I/O interface chip to support autonomous driving capabilities up to Level 4. This autonomous driving solution was first unveiled at Embedded World 2026 where it received the Embedded Award in the SoC/IP/IC Design category. The solution demonstrates XMotiv M3 performing safety orchestration, including system management and security functions.Moreover, the Physical AI Multi-Chiplet System. Get an exclusive preview of SiliconAuto's next-generation Physical AI inference solution. The solution is built on an automotive-grade high-performance computing (HPC) chiplet architecture, designed to meet the demanding requirements of future autonomous vehicles and advanced robotics platforms. The demonstration is powered by the SiliconPilot digital twin, which provides a pre-silicon model for validation and development.As Physical AI drives the emergence of autonomous vehicles and robots, SiliconAuto is helping customers bridge the gap between AI thinking and physical action. Through automotive-grade silicon solutions, built on XMotiv M3 microcontroller, high-performance computing (HPC) platforms, vehicle-to-everything connectivity solutions, and collaboration across Taiwan's world-leading semiconductor ecosystem, the company is enabling the next generation of safe and secure Physical AI systems. To know more about SiliconAuto, please visit during SEMICON Taiwan at Booth T9116, Level 7, TaiNEX Hall 2 or visit offcial webiste. 

Interested in knowing how to solve the microcrack problem in through-glass via (TGV) fabrication? Interested in knowing how to supply 1,000 Watts, 1 Volt and 1,000 Amperes electricity to semiconductor IC chips in an AI multichip package? Interested in knowing how to increase the glass panel size for manufacturing AI multichip packages? If so, visit iCometrue® at Booth M0957, Hall 1, 4F, Taipei Nangang Exhibition Center during SEMICON Taiwan 2026!Benefiting from their excellent thermal, mechanical, and electrical properties, glass substrates have emerged as a promising platform for large-size, high-performance AI multichip packages. At SEMICON Taiwan 2025 last year, iCometrue® exhibited the Through-Polymer-Via (TPV) Connector, a novel technology that provides vertical interconnection in Glass Cores for use in Glass Interposers and BGA substrates to solve the microcrack problem in glass substrates caused by TGV fabrication.At SEMICON Taiwan 2026 this year, iCometrue® plans to exhibit solutions for delivering over 1,000 W and over 200 A of power supply to the high-performance AI multichip package. The solutions include:(1) Embedding Cu Blocks in Glass Substrates for Power/Ground DeliveryCu blocks are used to replace TPVs/TGVs for power/ground delivery. This approach significantly reduces the number of TPVs/TGVs originally used for power/ground delivery through the glass substrate by 80%, thereby lowering fabrication complexity, improving manufacturing yield, and reducing manufacturing costs.A current high-performance AI multichip package, comprising GPU chips and HBM modules, has more than 10,000 I/Os for power, ground, signal, and clock distribution, which requires more than 10,000 TGVs/TPVs in the glass substrate. 80% of these TGVs/TPVs in the glass substrate are used for power/ground delivery. Using Cu blocks to replace TPVs/TGVs for power/ground delivery results in an 80% reduction in the number of TPVs/TGVs, thereby lowering fabrication complexity, improving manufacturing yield, and reducing manufacturing costs. Nowadays high-performance semiconductor IC chips in AI multichip packages typically require more than 1,000 W of power. Since power (P) is given by P=I×V, a 1 V operation voltage of semiconductor IC chips corresponds to a current over 1,000 A.As shown in Fig. 1, the embedded Cu blocks provide the power/ground voltage and current paths that would otherwise require a large number of TPVs or TGVs in the glass substrate. The remaining TPVs/TGVs (approximately 20%) are reserved for signal and clock transmission. Consequently, the embedded Cu blocks significantly reduce the number of TPVs/TGVs in the glass substrate.The formation of embedded Cu blocks in glass substrates is achieved by inserting Cu blocks into pre-formed large holes in the glass substrate. This process is similar to the TPV Connector embedding process in glass substrates previously disclosed at SEMICON Taiwan 2025.(2) Packaging Voltage Converter/Regulator (VCR) chips in AI Multichip PackagesThe VCR chips are packaged vertically under and close to the GPU chip within the AI multichip package. The embedded VCR chips convert the 1,000 W, 48 V, 21 A power supply from external circuits to 1,000 W, 1 V, 1,000 A for the GPU chip. As shown in Fig. 1, copper blocks provide a low resistance power delivery system from external circuits to the embedded VCR chips, and resulting in reduction of the heat generation.(3) Embedding Si Bridges, DTCs, and VCR chips in the Frontside Interconnection Scheme Over the Glass SubstrateAt SEMICON Taiwan 2025, iCometrue® demonstrated that Si bridges and DTCs are embedded in large holes within the glass substrate. Here in Fig. 1, iCometrue® shows that Si bridges, DTCs, and VCR chips are instead embedded in the frontside interconnection scheme over the glass substrate, while the TPV connectors and copper blocks are embedded in large holes in the glass substrate. This approach further simplifies the fabrication of the AI multichip package using a glass substrate.(4) Installing Electrical/Optical Connectors at the Edges of the AI Multichip PackageWhen glass substrates are used for multichip packaging, power and signals are usually input and output via the solder balls on the bottom of the multichip package through the backside interconnection (under the glass substrate), TPVs/TGVs (in the glass substrate), and the frontside interconnection (over the glass substrate) to the semiconductor chips. As discussed above, the fabrication of TPVs/TGVs is one of the major challenges in glass-substrate technology. To solve this problem, iCometrue® has introduced an innovative architecture that enables a large-size System-on-Panel (SOP) multichip package using a thick glass substrate without TPVs/TGVs.As shown in Fig. 2, power and signals are delivered through electrical and/or optical connectors located at the edges of the multichip package rather than through solder balls on the bottom of the package. The glass substrate is used as a panel-level fabrication platform and remains in the final package to provide mechanical support. An interconnection scheme (metal line and polymer) is built on the glass substrate, with electronic components such as interconnection bridges, integrated passive devices (IPDs), and VCR chips embedded within it. Semiconductor chips (CPU, GPU, ASIC, HBM) are then flip-chip bonded onto the interconnection scheme above the glass substrate. Electrical and/or optical connectors, together with passive components, are mounted on the top surface of the interconnection scheme using surface-mount technology (SMT).Credit:iCometrueBecause power and signals are supplied by the edge connectors instead of bottom solder balls, signal transmission and power distribution from the edge connectors to semiconductor chips are through the interconnection scheme. Consequently, no TPVs or TGVs are required in the glass substrate, enabling large-size System-on-Panel (SOP) packages. Further, since no TPVs or TGVs are required, a thicker glass substrate can be used, which greatly reduces the bending of the glass panel. Thereby, the size of the glass panel used in the fabrication can be greatly increased.More than Moore: The Use of Glass Substrates for Multichip PackagingiCometrue® is pioneering a new era of advanced multichip packaging by introducing glass substrates with embedded TPV Connectors and Cu blocks, providing a practical and scalable alternative to conventional TGV-based processes. Further, embedding Si bridges, DTCs, and VCR chips in the frontside interconnection scheme over the glass substrate simplifies the fabrication of the AI multichip package. Combined with the TPV/TGV-free thick glass substrate architecture for System-on-Panel (SOP) packaging, these technologies establish a foundation for the next generation of multichip integration, extending Moore's Law into the era of glass-based system packaging and accelerating the advancem