With these innovations, the Archer 300 LCM can serve as a comprehensive overlay error management solution throughout the fab, meeting the specifications
required to qualify scanners and tightly control high volume manufacturing of logic and memory devices, the company said.
The company said the implementation of novel extensions to 193i lithography has had an enormous impact on the overlay error allowance for critical layers. In particular, the use of double patterning lithography reduces the tolerable overlay error to just a few nanometers at the 32nm node, and subsequent nodes have an even smaller allowance.
Archer 300 LCM systems have been shipped to major memory and logic semiconductor manufacturers worldwide, where they will be used for overlay applications in advanced development and high-volume production, the company added.
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