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IDF San Francisco: Intel CEO displayed a silicon wafer built on 22nm process
Photo: Monica Chen [Sep 24, 2009]

Intel president and CEO Paul Otellini has displayed a silicon wafer containing its first working chips built on 22nm process technology. The 22nm test circuits include both SRAM memory as well as logic circuits to be used in future Intel processors, according to Intel.

The 22nm wafer displayed by Otellini is made up of individual die containing 364 million bits of SRAM memory and has more than 2.9 billion transistors packed into an area the size of a fingernail. The chips contain the smallest SRAM cell used in working circuits ever reported at 0.092-square microns, claimed Intel. The devices rely on a third-generation high-k metal gate transistor technology for improved performance and lower leakage power.

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