Co-packaged optics (CPO) has officially entered the mass-production deployment stage, but the critical testing processes responsible for safeguarding yield continue to face different challenges across Insertion 1 through Insertion 4.
Supply chain sources noted that conventional semiconductor electrical testing is typically measured in seconds. By comparison, Insertion 1 testing of photonic integrated circuits (PICs) can take more than 10 minutes for a single die. With a testing system costing millions of US dollars, the resulting testing costs remain too high to deliver sufficient commercial value for volume production.
A similar challenge exists at Insertion 2, which tests electronic-photonic integrated circuits (EPICs). Because the electronic IC (EIC) and PIC are integrated through hybrid bonding, creating an architecture with electrical circuitry above and photonics below, testing is constrained by limited industry experience in simultaneously testing both the electrical and optical sides. Wafer warpage presents another challenge, with testing times in some cases extending to as long as 30 minutes.
Yield ramp could ease early-stage testing bottleneck
Faced with these throughput constraints, industry sources believe the main reason is that the COUPE platform remains in the early stages of mass-production deployment. To ensure yield at each stage, suppliers initially tend to adopt a strategy of conducting 100% testing at every stage.
As PIC production moves through the yield-ramp phase, however, the problem of lengthy Insertion 1 testing is expected to gradually ease from 2027 onward.
That does not mean all CPO mass-production bottlenecks will be resolved. In addition to the concept of shifting testing left, industry players have also proposed a "shift-to-middle" approach, moving a critical CPO testing checkpoint to Insertion 3.
The reason lies in the compounding effect of defects. Even if PIC yield exceeds 98%, after the EPIC and fiber array unit (FAU) undergo optical alignment and coupling before being packaged into an optical engine, a failure in any one of the 16 internal channels could reduce optical-engine yield to just 52%.
In other words, roughly one out of every two optical engines produced could be defective.
To prevent defective products from progressing to the next manufacturing stage and being co-packaged with costly application-specific integrated circuit (ASIC) chips, Insertion 3 testing of the optical engine is therefore viewed as another critical line of defense.
Compared with earlier stages, Insertion 3 already has relatively mature mass-production solutions available, making testing less difficult to execute and requiring less time.
Insertion 4 remains unsettled as CPO test flows lack standardization
Supply chain sources also pointed out that after the optical engine and ASIC are integrated into a CPO module, the final Insertion 4 testing conducted before the module is incorporated into an end customer's product has yet to be finalized in terms of required test items and procedures. This could emerge as another major bottleneck for CPO mass production.
In addition to Ins4e, which is similar to conventional final testing (FT), the industry is pursuing several other approaches, including Ins4o, Ins4eo, and Ins4 SLT. Different suppliers are developing these solutions or advancing them through validation.
The range of approaches also underscores that CPO testing processes have yet to become standardized and could still change as end-customer requirements evolve.
Industry sources added that multiple CPO technology paths currently coexist in the market, with different ecosystems centered on end customers including Nvidia, Broadcom, and Marvell. With no "absolute winner" having emerged, suppliers developing related solutions must also contend with difficult decisions over which technology path to pursue and how to allocate R&D resources.
Article translated by Scarlett Yu and edited by Jack Wu
