Infineon Technologies and Fairchild Semiconductor have announced an agreement to create compatibility between their power MOSFET packages. Specifically the agreement covers the Infineon PowerStage 3x3 and Fairchild MLP 3x3 packages.

Thin-film integrated passive devices (IPDs) have the potential to extend wafer-level packaging and through-silicon via (TSV) technology to many IC package solutions and the discrete passive component industry. This market could expand from US$600 million this year to reach beyond US$1 billion by 2013.

With the forecast for packaging improving in 2010, business strategy is shifting toward more partnerships and joint ventures. And the focus on through-silicon vias (TSVs) is rapidly accelerating and may result in even more partnerships and joint ventures between foundries and packaging houses.

Applied Materials will acquire Semitool for up to US$364 million, positioning Applied in the growing markets of wafer-level packaging and copper memory interconnects.

IC packaging and testing service provider STATS ChipPAC has reported net income of US$25.1 million for third-quarter 2009, compared to profits of US$2.2 million in the prior quarter and US$7.9 million a year ago. Gross margin for the quarter reached 20.2% compared to 15.1% in the second quarter and 18.5% in third-quarter 2008.

In recent times, copper has been rapidly gaining a foothold as a substitute material for gold in wire bonding. Some of the advantages include superior electrical and thermal conductivity, less intermetallic compound growth and greater mechanical stability.

A new Microelectronics Innovation Center is being formed at the Université de Sherbrooke in Bromont, Québec, to focus on 200mm MEMS and 3D wafer-level packaging, and advanced technologies associated with the assembly and packaging of silicon chips.

MEMS packaging may take an evolutionary leap forward into wafer-level packaging, driven by large IDMs and foundries, analysts said. "TSMC (Hsinchu, Taiwan) and others are talking about making MEMS parts...and they have the resources to do the package too.

The past several semiconductor downturns have resulted in transitions from one generation of packaging to the next. This one's no exception.

The Jincheon site will manufacture silicone intermediate materials and encapsulants for LED packaging applications.

Tessera Technologies has said that it won a patent dispute over small-format semiconductor packaging products, with the International Trade Commission issuing a cease-and-desist order against rivals Motorola, Qualcomm, Freescale Semiconductor and Spansion.

The cost and performance benefits of flip-chip packaging, combined with the increased cost of gold bonding wire, have made flip-chip technology competitive for applications ranging from cell phones to gaming chips.

Semiconductor packaging/assembly/test companies are gently ratcheting up their manufacturing capacity, but it won't be enough to prevent a culling of the herd, with nearly 20 (mostly older) facilities likely to be shuttered within a span of two years, according to new analyses from Gartner.

Two white LED emitters have broken efficiency records, according to a National Institute of Standards and Technology (NIST) report released on December 8, 2008. Both emitters were developed by the Optoelectronics Packaging & Materials Labs at the University of California, Irvine, and both were made from blue LED chips available on the open market.

Innovative packaging of standard blue chips delivers almost 90 lm/W; professor claims 197 lm/W could be possible with state-of-the-art die.

Driven by increasing demand from mobile devices and automotive applications, wafer-level packaging (WLP) is moving up to higher I/O counts and finer pitches, experts said. Other WLP trends to watch in 2009 include high-power and high-accuracy precision devices, through-silicon vias (TSVs), fan-outs, and embedded flash.

STATS ChipPAC (Singapore), which provides semiconductor test and advanced packaging services, has responded to the global semiconductor downturn with a restructuring plan that results in ~1600 employees being laid off, ~12% of the company’s workforce.

Hyderabad's plan to become the semiconductor manufacturing capital of India has run into trouble and this could impact Andhra Pradesh's image as a vibrant investment destination. SemIndia, an integrated semiconductor company, has decided to put its plan to set up a US$3-billion chip manufacturing facility (fab) on the backburner. But the company's proposed plant on assembly, testing, marking and packing (ATMP) in the city will start production in the second quarter of next year.

The new QFN package family, referred to as QFNs-se, features a higher number of thin I/O terminal pads as compared to conventional single or dual row QFN or leadframe-based Quad Flat Packages (QFP). The QFNs-se can accommodate three or more rows of terminals in a fine fixed or variable pitch, providing a wider pin count range of 50 to 250 I/O as compared to standard QFN packages which have 4 to 156 I/O. The QFNs-se is also considered to be a cost effective alternative to lower ball count Fine Pitch Ball Grid Array (FBGA) packages.