Taipei, Tuesday, November 25, 2014 06:42 (GMT+8)
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Altera announces FPGA support for OpenCL
Michael McManus, DIGITIMES, Taipei [Tuesday 6 November 2012]

Altera has announced a software development kit (SDK) for OpenCL (Open Computing Language), for use with its FPGA, which combines the parallel architecture of an FPGA with the OpenCL parallel programming model. The SDK allows system developers and programmers familiar with C to quickly and easily develop high-performance, power-efficient FPGA-based applications in a high-level language. The Altera SDK for OpenCL enables FPGAs to work in concert with the host processor to accelerate parallel computation, at a much lower use of power compared to hardware alternatives.

The Altera SDK for OpenCL offers a unified, high-level design flow for hardware and software development that automates the time-consuming tasks required in typical hardware-design language (HDL) flows. The OpenCL tool flow automatically converts OpenCL kernel functions into custom FPGA hardware accelerators, adds interface IPs, builds interconnect logic and generates the FPGA programming file. The SDK includes libraries that link to OpenCL API calls within a host program running on the CPU. By automatically handling these steps, designers are able to focus their development efforts on defining and iterating their algorithms rather than designing hardware.

The portability of the OpenCL code enables users to migrate their designs to different FPGAs or SoC FPGAs as their application requirements evolve. With SoC FPGAs, the CPU host is embedded into the FPGA, providing a single-chip solution that delivers significantly higher bandwidth and lower latency between the CPU host and the FPGA compared to using two discrete devices.

The Altera SDK for OpenCL also enables programmers to leverage the massively parallel, fine-grained architectures featured in FPGAs to accelerate parallel computation. Unlike CPUs and GPGPUs, where parallel threads are executed across an array of cores, FPGAs allow kernel functions to be transformed into dedicated, deeply pipelined hardware circuits that are multithreaded using the concept of pipeline parallelism. Each of these pipelines can be replicated many times to provide even more parallelism by allowing multiple threads to execute in parallel. The result is an FPGA-based solution that Altera says can deliver >5X performance/Watt compared to alternative hardware implementations.

Altera is working with several board partners to deliver COTS board solutions to customers. Currently, boards from BittWare and Nallatech are designed to support Altera OpenCL. Additional third-party boards will be supported with future releases of the SDK.

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