Applied Materials introduced the industry's first use of ruthenium in high-volume production, enabling copper chip wiring to scale to the 2nm node and beyond while reducing resistance by up to 25%.
Additionally, the company developed an enhanced low-k dielectric material that reduces chip capacitance and strengthens logic and DRAM chips, facilitating advanced 3D stacking. Prabu Raja, president of the Semiconductor Products Group at Applied Materials, said that the rise of AI demands more energy-efficient computing, adding that Applied Materials' latest solutions address critical challenges in chip wiring and stacking, directly impacting performance and power consumption.
Modern logic chips contain billions of transistors interconnected by kilometers of microscopic copper wires. These wires are formed within thin dielectric films etched with channels filled with copper.
While this combination has been the industry standard for decades, further miniaturization has encountered obstacles. Thinner dielectrics weaken chips, and narrower copper wires increase resistance, hindering performance and efficiency.
According to the press release, Applied Materials' Black Diamond material has led the industry for decades, offering a low-dielectric-constant film that reduces electrical interference and power consumption. The company has introduced an enhanced version with an even lower k-value, facilitating scaling to 2nm and below. This new material also strengthens chips, which is essential for the future of 3D chip stacking.
Creating ever-smaller copper wires requires a precise layering process. To achieve this, Applied Materials' new IMS (Integrated Materials Solution) combines six technologies, including an industry-first material combination.
The binary metal liner, composed of ruthenium and cobalt (RuCo), reduces liner thickness by a third, creating void-free copper wires with lower resistance. This advancement translates to improved chip performance and lower power consumption.
Applied Materials said that leading chipmakers like Samsung and TSMC are already adopting these new technologies. They acknowledge reduced interconnect resistance's crucial role in achieving energy-efficient performance gains for AI computing.
