Improved testing is important, but cost is key. Healy cited Qualcomm as finding no problems in 61% of field returns; he attributed this to insufficient testing.
Because of current organization, DFT may be cut to save cost and speed time to market, but this may be a false saving. Small increases in design time can improve time to market and reduce cost of tests. With wafer-level testing at full speed (with BIST), yield at final test improves. This also means less testers as test times are faster.
DFT is a value play, not a cost play.
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- Silicon photonics set for takeoff (Oct 30) - EE Times
- TikTok founder becomes China's richest man (Nov 1) - BBC News
- Nvidia to take Intel's spot on Dow Jones Industrial Average (Nov 1) - Reuters
- Huawei's latest AI processors were made by TSMC (Oct 22) - Bloomberg
- Arm to scrap Qualcomm chip design license in feud escalation (Oct 23) - Bloomberg
- Embedded World brings 3,500 visitors to 1st US outing (Oct 11) - EE Times
- Preparing electronics engineering students for industry (Oct 8) - EETimes Europe
- Former Apple hardware chief Dan Riccio is retiring (Oct 11) - Ars Technica
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