On August 4, Powerchip Semiconductor Manufacturing Company (PSMC) unveiled the Logic-DRAM multi-layer wafer stacking technology and 2.5D interposers to meet rising AI demand.
PSMC stated that major companies, including AMD, will use the technology combined with advanced logic processes from leading foundries to develop high-bandwidth, high-capacity, low-power 3D AI chips. These chips are aimed at providing cost-effective, high-performance solutions for large language model AI applications and AI PCs.
According to PSMC, 3D AI chips produced with the new technology offer ten times the data transmission bandwidth and only one-seventh the power consumption compared to traditional AI chips, demonstrating exceptional performance for AI inference systems.
With expertise in both memory and logic process platforms, PSMC's recently developed Logic-DRAM technology has led to collaborations with AMD, Japanese GPU chip designers, and system integrators to produce 3D AI chips using advanced logic processes from leading foundries.
PSMC reported that by partnering with AP Memory Technology for customized DRAM chip designs and integrating Logic-DRAM multi-layer wafer stacking technology, the new 3D AI chips can deliver up to 100 times the transmission bandwidth per unit area compared to existing 2.5D AI chip architectures using High Bandwidth Memory (HBM). This makes them highly attractive for applications requiring enhanced performance, lower costs, and reduced power consumption in large language model (LLM) AI and AI PC markets.
Additionally, to support high-speed transmissions between GPU and HBM2E/3, PSMC's 2.5D interposers with high-density capacitor integrated passive device (IPD) products, developed according to customer needs, have been certified. Production lines are being set up at the Tongluo facility to meet customer demand and accelerate mass production.
