TSMC is advancing system-level innovation by improving the 3D IC design ecosystem through enhanced collaboration with foundries, customers, and partners, according to a recent blog post. The latest version of its 3Dblox standard has been further developed to more effectively address the challenges of large 3D IC design with early planning capabilities.
Introduced in 2022, TSMC's 3Dblox open standard has enabled EDA vendors to model critical physical stacking and logical connectivity information for 3D IC designs in a single format. 3Dblox simplifies 3D IC design by facilitating cross-tool interoperability and offering a comprehensive perspective on physical and logical connectivity.
TSMC reports that the 3Dblox standard has undergone numerous updates since its inception, increasing its accessibility to partners and customers with each iteration. In 2022, 3Dblox implemented a modular approach to the representation of all 3D IC architectures. Last year's improvement focused on enhancing the feasibility of prototyping for early architectural exploration.
The latest 3Dblox release includes major advancements such as AI-powered global resource optimization, multi-physics analysis convergence, early floorplan Design Rule Check (DRC), auto alignment marks insertion, and 3Dblox common constraints for early chip-package co-design.
Dan Kochpatcharin, head of TSMC's ecosystem and alliance management division, stated, "Working with our OIP ecosystem partners, we are utilizing AI and machine learning to significantly improve 3D IC design productivity and optimize design power, performance, area (PPA), and quality of results (QoR). As a proud member of the 3Dblox committee, we are working with other committee members to drive the next evolution of the 3Dblox standard, significantly boosting the 3D IC design efficiency and pushing the industry forward."
Enabling AI innovation
To meet the unprecedented demand for advanced silicon solutions capable of handling colossal datasets and computations amidst the rapid adoption of AI, the industry is pushing the boundaries of advanced process and 3D IC technologies. TSMC and its OIP ecosystem partners are at the forefront of this paradigm shift, working together to deliver advanced EDA and IP solutions utilizing TSMC's most advanced process and 3DFabric technologies to accelerate advancements in 3D IC design, fueling AI innovation.
"We work with OIP partners to certify their industry-leading digital and custom full design flow for implementation and signoff using the latest advanced 3nm and 2nm technologies, ensuring customers' successful tape-outs," Kochpatcharin wrote in the blog post.
TSMC's latest collaboration also includes TSMC-certified design platforms that support its 3DFabric technology, which incorporates SoIC and CoWoS, including the latest system-on-wafer packaging. This collaboration continues the tradition of design technology co-optimization by optimizing PPA on the latest TSMC technologies like N3 FinFLEX, N2 NanoFLEX, and the newest TSMC A16 with innovative backside power solutions to power future AI innovation.
Gary Szilagyi, VP of Annapurna Labs at AWS, was quoted in TSMC's blog post as stating, "Our collaboration with TSMC on advanced silicon solutions for our AWS-designed Nitro, Graviton, Trainium, and Inferentia chips enables us to push the boundaries of advanced process and packaging technologies, providing our customers with the best price-performance for virtually any workload running on AWS."
The blog post also cited Greg Dix, Broadcom's VP of R&D & Engineering for ASIC product, as stating, "Broadcom completed the successful bring-up of the industry's first Face-to-Face 3D SoIC in September 2024. This device uses TSMC's 5nm process, 3D die-stacking, and CoWoS packaging technologies to integrate 9x die(s) and 6x HBM stacks in a large package. This paves the way for a number of 3D-SoIC production ramps expected in 2025. Broadcom continues to use 3Dblox, which is a welcome advancement for interoperability of EDA tools in 3D IC design flow."
