TSMC announced at the Open Innovation Platform (OIP) Ecosystem Forum in Europe that its CoWoS packaging technology will achieve certification by 2027, introducing a version with 9x reticle size. This advancement will accommodate twelve HBM4 memory stacks, providing unprecedented performance enhancements for artificial intelligence (AI) and high-performance computing (HPC) chips.
According to Tom's Hardware, TSMC plans to launch the 9x reticle package in 2027, offering a space of 7,722 square mm. If certified in 2027, it is expected to be utilized in high-end AI processors between 2027 and 2028.
The CoWoS technology was first launched in 2016, initially featuring a package size of approximately 1.5x. Today, CoWoS has evolved to 3.3x reticle sizes, capable of accommodating eight HBM3 stacks.
TSMC anticipates employing SoIC vertical stacking logic chips to increase transistor count and performance. For instance, within the 9x reticle package, customers can stack 1.6nm process chips on top of 2nm chips.
ITHome reported that every year, TSMC introduces new process technologies to meet customer demands regarding power, performance, and area (PPA). For some customers, the 858 square mm currently offered by EUV lithography tools is not enough to support performance requirements.
TSMC has committed to launching a 5.5x reticle package between 2025 and 2026, which will support up to twelve HBM4 stacks.
However, ultra-large CoWoS packages face challenges related to substrate size and heat dissipation. For example, the 5.5x reticle version requires a substrate measuring 100x100mm, while the 9x reticle version exceeds 120x120mm. The large substrate sizes will impact system design and data center configurations, particularly concerning power supply and cooling systems.
In terms of power consumption, high-performance processors may reach several hundred kW per rack, making liquid cooling and immersion cooling technologies more effective for managing dissipated heat.
