With IT products such as smartphone and Internet of Things (IoT) devices being designed with considerations of high performance, low cost, low power consumption and small form factor, IC makers have been pushing 16/14nm processes and developing 10nm processes to satisfy demand. However, as Moore's Law starts slowing the pace of advancement, many IC makers have crossed into the packaging industry to continue to meet demand.
Taiwan Semiconductor Manufacturing Company's (TSMC) Chip on Wafer on Substrate (CoWoS) manufacturing process based on Through Si Via (TSV) for 2.5D chips finished development in the second half of 2011. The process has been used to manufacture Xilinx FPGAs and AMD GPUs but faced issues with its over-large IC area and high manufacturing costs. In response, the IC maker came out with Fan-out Wafer level Package (FOWLP) technology which it combined with the CoWoS manufacturing process to form its Integrated Fan-out (InFO) packaging solution.
In addition to TSMC, several other packaging service providers and IDMs such as Advanced Semiconductor Engineering (ASE), Amkor, STATS, Infineon, and Freescale have all developed their own FOWLP solutions.
Although FOWLP technology has advantages in terms of low cost, improved performance and small form factor, its integration level with the IC process and time to market are both weaker than those of PoP and SiP technologies. Therefore, some IC makers have started developing Wafer Level System in Package (WLSiP) technology using FOWLP technology as the base to further improve the integration level. Meanwhile, to further reduce costs and PCB usage area, Samsung Electronics has come out with an ePoP solution.
Digitimes Research expects the development of FOWLP technology to gradually advance to 3D chips and next-generation WLSiP technology. Meanwhile, development of TSV 3D IC integration technology is unlikely to show results until 2019-2020.
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