SEMI Japan president Masayuki Hamajima recently called for the semiconductor industry to unify packaging technology standards as soon as possible, particularly in the advanced packaging sector.
A recent Nikkei report cited Hamajima's remarks, emphasizing that establishing international standards for backend processes of major semiconductor manufacturers such as Intel, Samsung Electronics, and TSMC would effectively increase production capacity and address the current crunch of advanced packaging capabilities.
Yole Group projected in its recent research report that indicates that the advanced packaging market, driven by high-performance computing (HPC) and generative AI, is poised to achieve a compound annual growth rate (CAGR) of 12.9% over six years. Total revenue is estimated to increase from US$39.2 billion in 2023 to US$81.1 billion in 2029.
Yole's data showed that first-quarter 2024 revenue for advanced packaging reached US$10.2 billion, higher than the same period in 2023. The revenue for the second quarter is expected to climb further to US$10.7 billion, with the momentum of generative AI staying unabated.
Currently, the hottest application of advanced packaging is undoubtedly high bandwidth memory (HBM). By stacking multiple layers of DRAM on top of a logic chip, HBM achieves high-speed data transmission. The connection between each chip layer is made through through-silicon vias (TSV) and micro bumps, breaking the bandwidth bottleneck and becoming the preferred choice for AI training chips.
HBM adopts CoWoS packaging tech
The internal DRAM stacking within HBM is a form of 3D packaging, while the integration of HBM with AI GPUs and other accelerators on a silicon interposer is categorized as 2.5D packaging. Currently, HBM, steered by Nvidia and SK Hynix, primarily uses TSMC's CoWoS (chip-on-wafer-on-substrate) packaging technology.
TSMC developed the 2.5D packaging technology, CoWoS, as early as 2012. CoWoS can be divided into two steps: CoW (chip-on-wafer) and oS (on-substrate). The former is entirely completed by TSMC via its own production lines, while the latter has been partially outsourced to semiconductor assembly and test (OSAT) partners.
Under capacity constraints, TSMC and its customers can confidently entrust the oS portion to OSAT partners. However, the critical CoW portion differs from traditional packaging and testing processes, and "must" be completed on the front-end wafer manufacturing platform, essentially an extension of the front-end wafer manufacturing process.
This is evidently an inherent advantage for major foundry players like TSMC, Samsung, and Intel. Therefore, when Samsung and Intel saw TSMC thriving in the advanced packaging market and realized its tremendous growth potential, they naturally intensified the development of their new-generation advanced packaging technologies.
Currently, Samsung's self-developed advanced packaging technologies and services include I-Cube (2.5D) and X-Cube (3D). Intel is promoting its EMIB 2.5D packaging technology, which boasts a simple structure and low signal interference as EMIB's main advantages.
However, Samsung and Intel still lag behind TSMC in terms of yield, capacity, and commercialization levels for advanced processes below 5nm. For advanced packaging technologies that heavily rely on front-end wafer manufacturing technology and advanced process platforms, most HPC and AI chip customers prioritize TSMC for their wafer fabrication needs.
The current capacity crunch is partly due to most customers competing for TSMC's capacity. Meanwhile, the lack of international standards is not the primary reason why Samsung and Intel have not been able to secure more orders.
