Global Unichip Corp. (GUC), the Advanced ASIC Leader, today announced the successful launch of the industry's first Universal Chiplet Interconnect Express (UCIe) PHY silicon, achieving a data rate of 32 Gbps per lane, the highest speed defined in the UCIe specification. The 32G UCIe IP, supporting UCIe 2.0, delivers an impressive bandwidth density of 10 Tbps per 1 mm of die edge (5 Tbps/mm full-duplex). This milestone was achieved using TSMC's advanced N3P process and CoWoS packaging technologies, targeting AI, high-performance computing (HPC), xPU, and networking applications.
In this test chip, several dies with North-South and East-West IP orientations are interconnected through the CoWoS interposer. The silicon measurements show robust 32Gbps operation with wide horizontal and vertical eye openings. GUC is working aggressively on the full-corner qualification, and the complete silicon report is expected to be available in the coming quarter.
To ensure seamless system integration, GUC has developed bridges for AXI, CXS, and CHI buses utilizing the UCIe Streaming Protocol. These bridges are optimized for high traffic density, low power consumption, minimal data transfer latency, and efficient end-to-end flow control – enabling an effortless transition from traditional single-chip Networks-on-Chip (NoC) to chiplet-based architectures. Additionally, the bridges support Dynamic Voltage and Frequency Scaling (DVFS), allowing real-time voltage and frequency adjustments independently of each die without interrupting data flow.
GUC's UCIe IP also features advanced reliability capabilities, including UCIe Preventive Monitoring functionality and integrated I/O signal quality monitors from proteanTecs. This technology enables continuous, mission-mode monitoring of signal integrity during data transmission without the need for retraining or disrupting operations. Each signal lane is individually monitored, with real-time detection of power and signal integrity anomalies. Potential defects in bumps and traces are identified early, triggering repair algorithms that replace marginal I/Os with redundant ones to prevent system failures. This proactive approach significantly extends chip lifespan and enhances system reliability.
Pushing the boundaries of performance, GUC is committed to further increasing lane speeds while reducing power consumption. GUC has successfully taped out its second-generation UCIe IP, achieving 40 Gbps per lane in late 2024.
This new version incorporates Adaptive Voltage Scaling (AVS), delivering approximately 2x power efficiency improvements. In addition, a face-up version of the UCIe-40G IP, designed for 3D integration (SoIC) with Through-Silicon Vias (TSVs), is scheduled for tape-out in the coming months. Looking ahead, GUC's third-generation UCIe IP, capable of 64 Gbps per lane, is currently in development and slated for tape-out in the second half of this year. UCIe product line is optimized for all types of CoWoS and for future TSMC's SoW-X platform. "We are excited to announce the successful silicon bring-up of the world's first UCIe IP supporting 32 Gbps," said Aditya Raina, CMO of GUC.
"With a comprehensive, silicon-proven 2.5D/3D chiplet IP portfolio across TSMC's 7nm, 5nm, and 3nm process technologies, we deliver robust solutions that go beyond IP. Combined with our expertise in design, package engineering, electrical and thermal simulations, design-for-test (DFT), and production testing for TSMC's 3DFabric technologies, including CoWoS, InFO, TSMC-SoICR, we empower our customers to accelerate design cycles and achieve rapid bring-up of their AI, HPC, xPU, and networking products."
"We are committed to delivering the highest performance and lowest power 2.5D/3D chiplet and HBM interface IPs," said Igor Elkanovich, CTO of GUC. "The convergence of 2.5D and 3D packaging technologies, leveraging HBM3E/4/4E, UCIe, and UCIe-3D interfaces, enables the development of highly modular processors that exceed reticle size limitations, paving the way for the next generation of high-performance computing."
GUC UCIe-32G Silicon Highlights
√ 32Gbps per lane
√ Beachfront bandwidth density (full-duplex): 5Tbps/mm
√ AXI, CXS and CHI bus bridges
√ Dynamic Voltage and Frequency Scaling (DVFS)
√ UCIe Preventive Monitoring: per lane, in-mission mode I/O signal quality monitoring by protean Tecs
Article edited by Jack Wu
