Synopsys tapes out DesignWare, Interface IP for TSMC 7nm FinFET process

Jessie Shen, DIGITIMES, Taipei Wednesday 20 September 2017 0

Synopsys has announced the successful tape-out of a broad portfolio of DesignWare Foundation and Interface PHY IP for TSMC's 7nm process technology, including logic libraries, embedded memories, embedded test and repair, USB 3.1/2.0, USB-C 3.1/DisplayPort...

The article requires paid subscription. Subscribe Now

Email address

Password

Save my User ID and Password

Save my User ID and Password

Some subscribers prefer to save their log-in information so they do not have to enter their User ID and Password each time they visit the site. To activate this function, check the 'Save my User ID and Password' box in the log-in section. This will save the password on the computer you're using to access the site.

Note: If you choose to use the log-out feature, you will lose your saved information. This means you will be required to log-in the next time you visit our site.

NEW individual users please REGISTER first.

Enterprise user first-time LOGIN.

I forgot my ID and/or password?

MEMBERSHIP BENEFITS

Full access to articles dating back to 2000.
Real-time access to the news as it breaks.
Access to premium content.
Full access to Tomorrow's Headlines.
Asia Supply Chain 250 dataset access.